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AFE8000EVM: --> TSW14J58EVM Bringup process failing FPGA reset Error.

Part Number: AFE8000EVM
Other Parts Discussed in Thread: TSW14J58EVM, AFE8000

Hi TI,

I am currently running though the bring up process as provided with the AFE8000 connected to the TSW14J58EVM.

The Input ref signal to the LMK on the AFE8000 is correct to the bringup process. 

I am trying to go through the software "bring up" but I keep getting the error below in the log file and the error below*2 in the terminal.

Log file error:

"Resetting FPGA Pin.
Reset the FPGA and try again."

Terminal output error:

"ERROR Please check environment setup! No device is detected."

I have included the log file and the terminal output for completeness.

I have a feeling it may be to do with the referenced FTDI Not Connected but all 3 USBs are connected to SS connections.

AFE80xxCatLibrary
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
FPGA reset - USB Instrument created.
Power Card - USB Instrument created.
Version : 0x101204c
Connected to Capture Card
Loaded Libraries
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
#================ ERRORS:0, WARNINGS:0 ================#
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
Device Initialization for ChipVersion: 2.0
The External Sysref Frequency should be an integer factor of: 3.90625MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK and FPGA Configured.
DONOT_OPEN_Afe80xx_FULL - Device registers reset.
chipType: 0xa
chipId: 0x8001
chipVersion: 0x20
Programing FPGA ....
Resetting FPGA Pin.
Reset the FPGA and try again.
LMK and FPGA Configured.
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 9108
//PG Version = 1
//Release Date [dd/mm/yy] = 28/8/20
//Patch Version = 0
//PG Version = 0
//Release Date [dd/mm/yy] = 0/0/0
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE PAP and Alarms configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 11
Setting RBD to: 11
Programing FPGA ....
Resetting FPGA Pin.
Version : 0x101204c
Connected to Capture Card
FPGA Tx sysref captured
FPGA Rx sysref captured
Setting RBD to: 11
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1
###################################
AFE Configuration Complete
#================ ERRORS:3, WARNINGS:0 ================#
Loaded Configuration: AFE8000_SampleConfig.xlsx
Refreshed the GUI.
Device Initialization for ChipVersion: 2.0
The External Sysref Frequency should be an integer factor of: 3.90625MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 24750.0
laneRateRx1: 24750.0
laneRateFb: 24750.0
laneRateTx0: 24750.0
laneRateTx1: 24750.0
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
LMK and FPGA Configured.
DONOT_OPEN_Afe80xx_FULL - Device registers reset.
chipType: 0xa
chipId: 0x8001
chipVersion: 0x20
Programing FPGA ....
Resetting FPGA Pin.
Reset the FPGA and try again.
LMK and FPGA Configured.
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
//Firmware Version = 9108
//PG Version = 1
//Release Date [dd/mm/yy] = 28/8/20
//Patch Version = 0
//PG Version = 0
//Release Date [dd/mm/yy] = 0/0/0
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE PAP and Alarms configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 11
Setting RBD to: 11
Programing FPGA ....
Resetting FPGA Pin.
Version : 0x101204c
Connected to Capture Card
FPGA Tx sysref captured
FPGA Rx sysref captured
Setting RBD to: 11
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b10101010 . It is expected to be 0b10101010
BUF State TX0: 0b00000000 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1
###################################
AFE Configuration Complete
#================ ERRORS:3, WARNINGS:0 ================#
Connecting...
1
Detected 1 device(s) connected.
DEVICE[0]
        Flags = 4
        Type = 0
        ID = 0X0403601F
        LocId = 0
        SerialNumber = FT83SUUQ
        Description = TSW14J58
Creating
ftd3xx.ftd3xx.FTD3XX object at 0x000002441E3D7F28
Library Version 0X1030002
Driver Version 0X1030008
Firmware Version 0X000109
USB   784
True
Chip Configuration
        VendorID = 0x0403
        ProductID = 0x601f
        StringDescriptors
                Manufacturer = FTDI
                ProductDescription = TSW14J58
                SerialNumber = FT83SUUQ
        InterruptInterval = 0x09
        PowerAttributes = 0xa0 (Bus-powered Remote wakeup)
        PowerConsumption = 0x60
        Reserved2 = 0x00
        FIFOClock = 0x00 (100 MHz)
        FIFOMode = 0x01 (600 Mode)
        ChannelConfig = 0x02 (1 Channel)
        OptionalFeatureSupport = 0x0000
                BatteryChargingEnabled   0
                DisableCancelOnUnderrun  0
                NotificationEnabled      0 0 0 0
                UnderrunEnabled          0 0 0 0
                EnableFifoInSuspend      0
                DisableChipPowerdown     0
        BatteryChargingGPIOConfig = 0x0
        FlashEEPROMDetection = 0x10 (read-only)
                Custom Config Validity   Valid
                Custom Config Checksum   Valid
                GPIO Input               Ignore
                Config Used              Custom
        MSIO_Control = 0x00010800
        GPIO_Control = 0x00000000

Connected
Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Instantiated Class lmkLib
Instantiated Class fpgaLib_J58
Instantiated Class RRFLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class FbDigLib
Instantiated Class AGCLib
Instantiated Class FbDDCLib
Instantiated Class FbDGCLib
Instantiated Class FbDSAGPEC
Instantiated Class FbDCCorrLib
Instantiated Class FbPrgmDlyLib
Instantiated Class FbNLCLib
Instantiated Class FbDCEstimLib
Instantiated Class RxFbDsaLib
Instantiated Class TTLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class RRFLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class RxDigLib
Instantiated Class AGCLib
Instantiated Class RxDDCLib
Instantiated Class RxDSAGPEC
Instantiated Class ALCLib
Instantiated Class RxNLCLib
Instantiated Class RxDCCorrLib
Instantiated Class RxDGCLib
Instantiated Class RxPrgmDlyLib
Instantiated Class RxFbDsaLib
Instantiated Class FbDigLib
Instantiated Class AGCLib
Instantiated Class FbDDCLib
Instantiated Class FbDGCLib
Instantiated Class FbDSAGPEC
Instantiated Class FbDCCorrLib
Instantiated Class FbPrgmDlyLib
Instantiated Class FbNLCLib
Instantiated Class FbDCEstimLib
Instantiated Class RxFbDsaLib
Instantiated Class TTLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TxDigLib
Instantiated Class TxILIQCorrLib
Instantiated Class TopLib
Instantiated Class pllLib
Instantiated Class TimingController
Instantiated Class IoWrapLib
Instantiated Class JESDLib
Instantiated Class DACJesdLib
Instantiated Class DACJesdLib
Instantiated Class ADCJesdLib
Instantiated Class ADCJesdLib
Instantiated Class serdesLib
Instantiated Class serdesLib
Instantiated Class jesdSubchipLib
Instantiated Class DsaLib
Instantiated Class TopProcLib
Instantiated Class CalibTopHw
Instantiated Class MacroLib
Instantiated Class MacroHWLib
Instantiated Class MacroErrLib
Instantiated Class MacroHWLib
Instantiated Class DProc1Lib
Instantiated Class DProc1FwProgLib
Instantiated Class DProc1FwDbgLib
Instantiated Class DProc1MailboxLib
Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Instantiated Class cpldLib
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Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
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Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Deleting Handle..
Connecting...
0
ERROR Please check environment setup! No device is detected.
FTDI Not Connected
FPGA not connected. Function reset skipped.
FPGA not connected. Function checkVersion skipped.
FPGA not connected. Function fpgaTxConfig skipped.
FPGA not connected. Function selectDrive skipped.
FPGA not connected. Function fpgaRxConfig skipped.
FPGA not connected. Function selectCapture skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
Deleting Handle..
Connecting...
1
Detected 1 device(s) connected.
DEVICE[0]
        Flags = 4
        Type = 0
        ID = 0X0403601F
        LocId = 0
        SerialNumber = FT83SUUQ
        Description = TSW14J58
Creating
ftd3xx.ftd3xx.FTD3XX object at 0x000002442FFF5F60
Library Version 0X1030002
Driver Version 0X1030008
Firmware Version 0X000109
USB   784
True
Chip Configuration
        VendorID = 0x0403
        ProductID = 0x601f
        StringDescriptors
                Manufacturer = FTDI
                ProductDescription = TSW14J58
                SerialNumber = FT83SUUQ
        InterruptInterval = 0x09
        PowerAttributes = 0xa0 (Bus-powered Remote wakeup)
        PowerConsumption = 0x60
        Reserved2 = 0x00
        FIFOClock = 0x00 (100 MHz)
        FIFOMode = 0x01 (600 Mode)
        ChannelConfig = 0x02 (1 Channel)
        OptionalFeatureSupport = 0x0000
                BatteryChargingEnabled   0
                DisableCancelOnUnderrun  0
                NotificationEnabled      0 0 0 0
                UnderrunEnabled          0 0 0 0
                EnableFifoInSuspend      0
                DisableChipPowerdown     0
        BatteryChargingGPIOConfig = 0x0
        FlashEEPROMDetection = 0x10 (read-only)
                Custom Config Validity   Valid
                Custom Config Checksum   Valid
                GPIO Input               Ignore
                Config Used              Custom
        MSIO_Control = 0x00010800
        GPIO_Control = 0x00000000

Connected
(32, 396000.0)
(1, 12375.0)
PLL Rate Configured  12375.0
('DRP Read  ', '00000018')
0001310C 00000008

('DRP Write  ', '00000018  00000008')

('DRP Read  ', '00000018')
0001310C 00000020

('DRP Write  ', '00000018  00000020')

99.0
Selected OUTDIV   1
Selected HalfRate 1
Selected N        99
0001300C 00000008
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
00013008 00000002
('DRP Write  ', '0000000E  00000001')

('DRP Write  ', '0000000E  00000001')

00016008 00000002
('DRP Write  ', '0000000E  00000001')

('DRP Write  ', '0000000E  00000001')

Common
00013008 00000002
Select interface
('DRP Read  ', '0000000E')
0001310C 00000001

('HALFRATE ', 1)
('DRP Read  ', '00000014')
0001310C 00000061

('FBDIV', 97)
('DRP Write  ', '00000014  00000061')

('DRP Write  ', '00000014  00000061')

00016008 00000002
('DRP Read  ', '0000000E')
0001610C 00000001

('HALFRATE ', 1)
('DRP Read  ', '00000014')
0001610C 00000061

('FBDIV', 97)
('DRP Write  ', '00000014  00000061')

('DRP Write  ', '00000014  00000061')

('TX Lanes  ', [5])
TX_SW0  00000000
TX_SW1  00000000
StreamConfig  00060033
Stream 0  24.0115.2 Gbps 20.83%
Stream 1  0115.2 Gbps 0.00%
00010004 00020000
00011020 00000000
00012020 00000000
00011060 00000002
00012060 00000032
Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Opened the USB FTDI Handle.
Closing the USB FTDI Handle.
Deleting Handle..
Connecting...
0
ERROR Please check environment setup! No device is detected.
FTDI Not Connected
FPGA not connected. Function reset skipped.
FPGA not connected. Function checkVersion skipped.
FPGA not connected. Function fpgaTxConfig skipped.
FPGA not connected. Function selectDrive skipped.
FPGA not connected. Function fpgaRxConfig skipped.
FPGA not connected. Function selectCapture skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
FPGA not connected. Function fpgaJesdReset skipped.
FPGA not connected. Function fpgaSysref skipped.
FPGA not connected. Function fpgaSysrefCheck skipped.
Deleting Handle..
Connecting...
1
Detected 1 device(s) connected.
DEVICE[0]
        Flags = 4
        Type = 0
        ID = 0X0403601F
        LocId = 0
        SerialNumber = FT83SUUQ
        Description = TSW14J58
Creating
ftd3xx.ftd3xx.FTD3XX object at 0x000002442D8A4F28
Library Version 0X1030002
Driver Version 0X1030008
Firmware Version 0X000109
USB   784
True
Chip Configuration
        VendorID = 0x0403
        ProductID = 0x601f
        StringDescriptors
                Manufacturer = FTDI
                ProductDescription = TSW14J58
                SerialNumber = FT83SUUQ
        InterruptInterval = 0x09
        PowerAttributes = 0xa0 (Bus-powered Remote wakeup)
        PowerConsumption = 0x60
        Reserved2 = 0x00
        FIFOClock = 0x00 (100 MHz)
        FIFOMode = 0x01 (600 Mode)
        ChannelConfig = 0x02 (1 Channel)
        OptionalFeatureSupport = 0x0000
                BatteryChargingEnabled   0
                DisableCancelOnUnderrun  0
                NotificationEnabled      0 0 0 0
                UnderrunEnabled          0 0 0 0
                EnableFifoInSuspend      0
                DisableChipPowerdown     0
        BatteryChargingGPIOConfig = 0x0
        FlashEEPROMDetection = 0x10 (read-only)
                Custom Config Validity   Valid
                Custom Config Checksum   Valid
                GPIO Input               Ignore
                Config Used              Custom
        MSIO_Control = 0x00010800
        GPIO_Control = 0x00000000

Connected
(32, 396000.0)
(1, 12375.0)
PLL Rate Configured  12375.0
('DRP Read  ', '00000018')
0001310C 00000008

('DRP Write  ', '00000018  00000008')

('DRP Read  ', '00000018')
0001310C 00000020

('DRP Write  ', '00000018  00000020')

99.0
Selected OUTDIV   1
Selected HalfRate 1
Selected N        99
0001300C 00000008
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001320C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001320C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001320C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001320C 000000C0

('DRP Write  ', '00000063  000000C0')
('DRP Read  ', '0000007C')
0001620C 00002068

('TXOUT', '0x2068')
('DRP Read  ', '00000063')
0001620C 000000C0

('RXOUT', '0xc0')
('DRP Read  ', '0000007C')
0001620C 00002068

('DRP Write  ', '0000007C  00002068')
('DRP Read  ', '00000063')
0001620C 000000C0

('DRP Write  ', '00000063  000000C0')
00013008 00000002
('DRP Write  ', '0000000E  00000001')

('DRP Write  ', '0000000E  00000001')

00016008 00000002
('DRP Write  ', '0000000E  00000001')

('DRP Write  ', '0000000E  00000001')

Common
00013008 00000002
Select interface
('DRP Read  ', '0000000E')
0001310C 00000001

('HALFRATE ', 1)
('DRP Read  ', '00000014')
0001310C 00000061

('FBDIV', 97)
('DRP Write  ', '00000014  00000061')

('DRP Write  ', '00000014  00000061')

00016008 00000002
('DRP Read  ', '0000000E')
0001610C 00000001

('HALFRATE ', 1)
('DRP Read  ', '00000014')
0001610C 00000061

('FBDIV', 97)
('DRP Write  ', '00000014  00000061')

('DRP Write  ', '00000014  00000061')

('TX Lanes  ', [5])
TX_SW0  00000000
TX_SW1  00000000
StreamConfig  00060033
Stream 0  24.0115.2 Gbps 20.83%
Stream 1  0115.2 Gbps 0.00%
00010004 00020000
00011020 00000000
00012020 00000000
00011060 00000002
00012060 00000032

I have had these boards working in the past but they have all of a sudden become extremely difficult to get working.

Any help would be greatly appreciated.

Kind regards

Oliver Forbes-Shaw

  • Hi Oliver,

    Nice to see you again.

    Are you providing 5V at the header jack of the TSW14J58? I specify at the header jack to account for any cable losses.

    If you are using the cables that come with the EVM, could you try setting your power supply limits to 5.5V and 5A?

    Best,

    Camilo

  • Hi Camilo,

    Great to hear from you too!!

    I have popped down to the lab to double check and I can confirm the settings for the power supply are 5.5VDC and 5A.

    I am using the provided cable and have measured the voltage being received at the jack that connects to the read/write card is 5.5V.

    I tried the normal "bring up" and I am having the same issues as the scripts above, what do you advise I check next ?

    Kind regards

    Oliver

  • Hi Oliver,

    Ok, do you have the USB cables from the TSW14J58 connected to a USB hub? If yes, could you try connecting the two USB cables from the TSW14J58 straight into the PC? We have had some people have issues with the USB hubs.

    Best,

    Camilo

  • Hi Camilo,

    I have tried connecting both of the the TSW14J58 USB cables to the laptop and unfortunately I get the same results.

    I have also re-installed a fresh version of the "AFE80xxCat" software and the same results.

    What do you advise I should do next?

    Kind regards

    Oliver Forbes-Shaw

  • Hi Oliver,

    This is a bit odd, because from the log you have provided the GUI detects the TSW14J58 initially. But when it starts the configuration it can't find it. Here are some suggestions:

    1. When programming the AFE8000, after you see the error “Reset the FPGA and try again” appear. Could you try the following:
      1. Stop the run by pressing F10 (Or going to Run > Stop in the top left of the GUI.
      2. Run the command “myfpga.Reconnect()”
        1. If the GUI does not detect the FPGA, could you please reset the TSW14J58, reconnect the USBs connected to the TSW14J58 and try the command again until it can recognize the FPGA.
      3. Then start the bringup by clicking “Device Bringup”
    2. Do you have access to a USB to JTAG connector? If you do, could you try reloading the JESD204C firmware into the TSW14J58 by following the instructions in the “TSW14J58EVM_JESD204C_Firmware_EEPROM_Programming” folder in the secure folder?
    3. Another thing to try if possible would be to swap all of the USB cables in case one of them is damaged.

     Best,

    Camilo

  • Hi Camilo,

    I have tried:

    1. I got a mixed of it connecting straight away and other times requiring a power up and power down of the hardware to get it to connect again.

    2. I managed to get a hold of a USB to JTAG and followed the process to reload the FPGAs firmware. The average result was that when the fpga reset command in initiated the software holds there until it becomes non responsive.

    3. I have tried swapping the type A to mini USBs and no change, I am trying to find a type A to USB 3.0 Micro-B

    I am not sure where to go from here. Are there any specific jumpers that need to be in a specific orientation that I could be missing?

    Kind regards

    Oliver

  • Hi Oliver,

    Could you confirm if the jumpers on your TSW14J58 follow the default positions from the table below:

    Best,

    Camilo

  • Hi,

    Closing this post as we have taken this to email.

    Best,

    Camilo