AFE7900EVM: SPI INTERFACE

Soumya Mishra

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900

1) We have established the link between ADC(AFE7900EVM) and FPGA (Stratix 10 EVM) through GUI and then we tried SPI interface with SPIB1 with Hardware changes R82, R84, R85 & R44 are shorted, but we couldn't get the SDOUT from the ADC. So, after referring below forum, we tried through SPIA Interface.

AFE7900EVM: AFE7900EVM and TSW14J57EVM pin-mapping over FMC - RF & microwave forum - RF & microwave - TI E2E support forums

2) In addition to above changes we have done changes in hardware for SPIA Interface

Shorted: R88, R87, R86 and R83 for SPIA interface and R9 & R13 for FMC to FPGA connection.

Removed: R266, R267, R268 and R274

Log file generated registers are used for SPI programming. But we are not able to get the link between ADC and FPGA. Registers used and signal tap are attached for reference.

Still LMK is programmed through USB.

Kindly Suggest

Regards,

Soumya

Fullscreen Register_file.txt Download

over 1 year ago

0 Camilo Garcia Trujillo over 1 year ago

TI__Expert 5055 points

Hi Soumya,

Sorry for the delay.

In regards to question 1, like the post said, only SPIA is functional on reset of AFE7900. SPIB1 and SPIB2 ports have to configured to function as SPI ports through SPIA.

In regards to question 2:

If you shorted R9 & R13 you will have two SPIASDO and two SPIASEN pins on the FMC. We would suggest disconnecting whichever two the FPGA is not driving to avoid bus contention.

Could you provide what JESD errors are reported by your FPGA? Any LOS errors?
When programing the AFE do you see any changes in the current consumption?
Before programming did you do a hardware, reset to the AFE as required? This can be done by either pressing SW1 in the AFE7900EVM or by controlling the reset from the FPGA. To control the reset through the FPGA you must remove R94 and populate R93 in the AFE7900EVM.

Best,

Camilo

0 Soumya Mishra over 1 year ago

Prodigy 50 points

Hi Camilo,

1. After Removing R11, R14 Resistor we are able to resolve the bus contention issue.

2. The JESD errors are reported by FPGA are:

- Running disparity error and 8B/10B block PCS are not successfully decoding the incoming characters from the ADC.

- ADC is not transmitting K Character or BC Hexadecimal number to FPGA. Which starts the CGS Phase.

3. After programming the ADC, at the initial condition current consumption is 0.8 to 1 Amp and at the final stage (around at the last 100's Registers) current varies from 1.1 to 1.2 Amp and stabilizing at 1.2 Amp's.

4. Before Programming the AFE, we are controlling the RESET from FPGA with necessary changes (Removing R94 Resistor).

5. we are not able to receiver the 0xBC character from the ADC as we are not able to read proper data from the below registers. Indexes are from attached txt file of spi write registers:

a. Index:10247 (0x00f0), read data 0xff. --Read operation

b. Index:10276 (0x00f0), read data 0xff. --Read operation

c. Index:11368 (0x00f0), read data 0x00. -- poll check

d. Index:11379 (0x00f0), read data 0x00. -- poll check

e. Index:11408 (0x00f0), read data 0x00. -- poll check

For reference errors screenshot and Registers used for programming are attached.

Anticipating your prompt reply.

Regards,

Soumya

spi_write_c_code.txt

0 Camilo Garcia Trujillo over 1 year ago in reply to Soumya Mishra

TI__Expert 5055 points

Hi Soumya,

Glad that was able to resolve the SPI issue. To continue the debugging, we have the following questions:

You said this configuration had worked before correct? Do you have the python file so that we can check this on our EVM?

If there are any read check and/or poll fail during configuration we must address those first. Is the read on line 10247 the first read check or poll error you see? If yes, do you see it fail all the time at this step?

Best,

Camilo

0 Soumya Mishra over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 50 points

Hi Camilo,

Yes, this configuration has worked through GUI.

Yes, the first Error in Read and poll check is started with line 10247 and this fail is consistence for all the time for above 5 registers.

Python code is attached for your reference.

Fullscreen SCRIPT_FOR_SPI_REGISTERS.txt Download

sysParams							=AFE.systemParams
setupParams.skipFpga 				= 1
#setupParams.fpgaRefClk 				= 245.76	
setupParams.fpgaRefClk 				= 368.64
#setupParams.fpgaRefClk 				= 184.32
AFE.systemStatus.loadTrims			= 1

sysParams.FRef                    	= 491.52
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 8847.36
sysParams.rxEnable                  =[True,False,True,False]
sysParams.fbEnable                  =[False,False]
sysParams.txEnable                  =[False,False,False,False]
sysParams.enableDacInterleavedMode	= False 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
#sysParams.LMFSHdRx                	=['24410', '24410', '24410', '24410']	
sysParams.LMFSHdRx                	=['12610', '12610', '12610', '12610']	
#sysParams.LMFSHdRx                	=['12810', '12810', '12810', '12810']	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
#sysParams.LMFSHdFb                	= ["12810","12810"]
sysParams.LMFSHdFb                	= ["12610","12610"]
#sysParams.LMFSHdFb                	= ["12410","12410"]
sysParams.LMFSHdTx                	= ["24410","24410","24410","24410"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.txDataMux					= [2,3,0,1,4,5,6,7]
sysParams.jesdRxRbd					= [4, 4]

sysParams.rxJesdTxScr				= [False,False,False,False]
sysParams.fbJesdTxScr				= [False,False]
#sysParams.jesdRxScr					= [True,True,True,True]
sysParams.jesdRxScr					= [False,False,False,False]
#sysParams.serdesTxLanePolarity		= [False,False,False,False,False,False,False,False]
sysParams.serdesTxLanePolarity		= [True,True,True,True,True,True,True,True]

sysParams.rxJesdTxK					= [32,32,32,32]
sysParams.fbJesdTxK					= [32,32]
sysParams.jesdRxK					= [32,32,32,32]

sysParams.ncoFreqMode 				= "1KHz"

# NCO 0 SETTINGS 

sysParams.txNco0					= 	[[3200,3200],		#Band0, Band1 for TxA for NCO0
										[3200,3200],        #Band0, Band1 for TxB for NCO0
										[3200,3200],        #Band0, Band1 for TxC for NCO0
										[3200,3200]]        #Band0, Band1 for TxD for NCO0
										
sysParams.rxNco0					= 	[[3200,3200],		#Band0, Band1 for RxA for NCO0
										[3200,3200],        #Band0, Band1 for RxB for NCO0
										[3200,3200],        #Band0, Band1 for RxC for NCO0
										[3200,3200]]        #Band0, Band1 for RxD for NCO0

sysParams.fbNco0					= 	[3200,3200]			#FBA, FBC for NCO0

# ADDED ON 02-11-23 NCO 1 SETTINGS 

# sysParams.txNco1					= 	[[3100,3100],		#Band0, Band1 for TxA for NCO0
# 										[3100,3100],        #Band0, Band1 for TxB for NCO0
# 										[3100,3100],        #Band0, Band1 for TxC for NCO0
# 										[3100,3100]]        #Band0, Band1 for TxD for NCO0
# 										
# sysParams.rxNco1					= 	[[3100,3100],		#Band0, Band1 for RxA for NCO0
# 										[3100,3100],        #Band0, Band1 for RxB for NCO0
# 										[3100,3100],        #Band0, Band1 for RxC for NCO0
# 										[3100,3100]]        #Band0, Band1 for RxD for NCO0
# 
# sysParams.fbNco1					= 	[3100,3100]			#FBA, FBC for NCO0


# # our working nco
# sysParams.txNco0					= 	[[2698.24,2698.24],		#Band0, Band1 for TxA for NCO0
# 										[2698.24,2698.24],        #Band0, Band1 for TxB for NCO0
# 										[2698.24,2698.24],        #Band0, Band1 for TxC for NCO0
# 										[2698.24,2698.24]]        #Band0, Band1 for TxD for NCO0
# 
# sysParams.rxNco0					= 	[[2698.24,2698.24],		#Band0, Band1 for RxA for NCO0
# 										[2698.24,2698.24],        #Band0, Band1 for RxB for NCO0
# 										[2698.24,2698.24],        #Band0, Band1 for RxC for NCO0
# 										[2698.24,2698.24]]        #Band0, Band1 for RxD for NCO0
# 
# sysParams.fbNco0					= 	[2698.24,2698.24]			#FBA, FBC for NCO0

# c band
#sysParams.txNco0					= 	[[5850,5850],		#Band0, Band1 for TxA for NCO0
#										[5850,5850],        #Band0, Band1 for TxB for NCO0
#										[5850,5850],        #Band0, Band1 for TxC for NCO0
#										[5850,5850]]        #Band0, Band1 for TxD for NCO0

#sysParams.rxNco0					= 	[[5850,5850],		#Band0, Band1 for RxA for NCO0
#										[5850,5850],        #Band0, Band1 for RxB for NCO0
#										[5850,5850],        #Band0, Band1 for RxC for NCO0
#										[5850,5850]]        #Band0, Band1 for RxD for NCO0

#sysParams.fbNco0					= 	[5850,5850]			#FBA, FBC for NCO0




sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

#sysParams.ddcFactorRx             	= [48,48,48,48]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorRx             	= [24,24,24,24]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [24,24]
sysParams.ducFactorTx             	= [36,36,36,36]


## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	3.84
#lmkParams.sysrefFreq				=	1.92
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x00
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 1
sysParams.jesdCDLvdsSync			= 1
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True
sysParams.serdesFirmware			= True




# ## The following parameters sets up the AGC
## CHANNEL A
#sysParams.agcParams[0].agcMode = 2 ##internal AGC-1,external agc-4 pin configuration-3
#sysParams.agcParams[0].en_agcfreeze_pin = 0 #Enable or Disable pin based AGC freeze.
#sysParams.agcParams[0].tdd_freeze_agc = 1 #1: Freeze Whether to reset or freeze the attack detectors during the OFF period of TDD
#sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
#sysParams.agcParams[0].atken = [0,1,0] ##enable big and small step attack
#sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
#sysParams.agcParams[0].atksize = [1,2] ## bigs step = 2dB, small step = 1dB
#sysParams.agcParams[0].decaysize = [1,2] ##big step = 2dB, small step = 1dB
#sysParams.agcParams[0].atkthreshold = [-1,-2,-14] ##attack threshold
#sysParams.agcParams[0].decaythreshold = [-14,-8,-20]  ##decay threshold
#sysParams.agcParams[0].atkwinlength = [170,170]  ## detector time constant expressed inn absolute time in ns. 
#sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
#sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
#sysParams.agcParams[0].decayNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
#sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
#sysParams.agcParams[0].maxDsaAttn = 4 ##maximum DSA attenuation used by AGC
#sysParams.agcParams[0].totalGainRange = 4 ##total gain range used by ALC for gain compensation
#sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
#sysParams.agcParams[0].useMinAttnAgc = 0 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
#sysParams.agcParams[0].alcEn = 0
#sysParams.agcParams[0].alcMode = 0 ##floating point DGC
#sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
#sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent

#sysParams.agcParams[0].pkDetPinLsbSel =0
#sysParams.agcParams[0].pkDetOnPenultimateLsb =0

## CHANNEL C
#sysParams.agcParams[2].agcMode = 2 ##internal AGC-1,external spi configuration-2,external agc-4 pin configuration-3
#sysParams.agcParams[2].en_agcfreeze_pin = 0 #Enable or Disable pin based AGC freeze.
#sysParams.agcParams[2].tdd_freeze_agc = 1 #1: Freeze Whether to reset or freeze the attack detectors during the OFF period of TDD
#sysParams.agcParams[2].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
#sysParams.agcParams[2].atken = [0,1,0] ##enable big and small step attack
#sysParams.agcParams[2].decayen = [0,1,0] ##enable big and small step decay
#sysParams.agcParams[2].atksize = [1,2] ## bigs step = 2dB, small step = 1dB
#sysParams.agcParams[2].decaysize = [1,2] ##big step = 2dB, small step = 1dB
#sysParams.agcParams[2].atkthreshold = [-1,-2,-14] ##attack threshold
#sysParams.agcParams[2].decaythreshold = [-14,-8,-20]  ##decay threshold
#sysParams.agcParams[2].atkwinlength = [170,170]  ## detector time constant expressed inn absolute time in ns. 
#sysParams.agcParams[2].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
#sysParams.agcParams[2].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
#sysParams.agcParams[2].decayNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
#sysParams.agcParams[2].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
#sysParams.agcParams[2].maxDsaAttn = 4 ##maximum DSA attenuation used by AGC
#sysParams.agcParams[2].totalGainRange = 4 ##total gain range used by ALC for gain compensation
#sysParams.agcParams[2].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
#sysParams.agcParams[2].useMinAttnAgc = 0 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
#sysParams.agcParams[2].alcEn = 0
#sysParams.agcParams[2].alcMode = 0 ##floating point DGC
#sysParams.agcParams[2].fltPtMode = 0 ##if exponent > 0, dont send MSB
#sysParams.agcParams[2].fltPtFmt = 1 ##3 bit exponent
#sysParams.agcParams[2].pkDetPinLsbSel =0
#sysParams.agcParams[2].pkDetOnPenultimateLsb =0

## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'ADC_SYNC1',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'DAC_SYNC0',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD'],
		#'G16': ['RX_NCOSEL_0','RX_NCOSEL_1'],# ADDED ON 02-11-23
		#'L14': ['TX_NCOSEL_0','TX_NCOSEL_2'],# ADDED ON 02-11-23
#		'H11': ['TX_NCOSEL_0','TX_NCOSEL_2'],
#		'H16': ['FB_NCOSEL_0','FB_NCOSEL_2']
	}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
	

	
## Initiates LMK04828 and AFE79xx Bring-up
setupParams.skipLmk	=	False

AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()
## Initiates AFE79xx Bring-up
setupParams.skipLmk	=	True
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)

### ADC Ramp Out
for i in range(3):
	AFE.JESD.ADCJESD[0].adcRampTestPattern(i,1,1)
	AFE.JESD.ADCJESD[1].adcRampTestPattern(i,1,1)

#AFE.JESD.ADCJESD[0].adcRampTestPattern(i,0,1)
#AFE.JESD.ADCJESD[1].adcRampTestPattern(i,0,1)

# val=20
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_TEST_PATTERN_CTRL.rx1_jesd_test_sig_gen_mode=1
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_TEST_PATTERN_CTRL.rx2_jesd_test_sig_gen_mode=1
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_TEST_PATTERN_CTRL.rx1_jesd_test_sig_gen_mode=1
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_TEST_PATTERN_CTRL.rx2_jesd_test_sig_gen_mode=1

# 
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input0=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input1=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input2=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input3=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input4=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input5=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input6=val
# device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input7=val
# 
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input0=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input1=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input2=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input3=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input4=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input5=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input6=val
# device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input7=val
#
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input0=0x1122
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input1=0x3344
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input2=0x5566
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input3=0x7788
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input4=0x99AA
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input5=0xBBCC
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input6=0xCCDD
device.JESD.ADC_JESD[0].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input7=0xEEFF

device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input0=0x0102
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input1=0x0304
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input2=0x0506
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input3=0x0708
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input4=0x090A
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input5=0x0B0C
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input6=0x3344
device.JESD.ADC_JESD[1].ADC_JESD.ADC_JESD_SHORT_TEST_PATTERN.jesd_short_test_pattern_input7=0x3344

### DSA Settings

# working code
for i in range(4):
	AFE.DSA.setRxDsa(i,10)

#Relinks ADC and DAC links.
#If pinSysref is 0, internal copy of sysref is used for relinking.
#If pinSysref is 1, pin based sysref is used for linking.
AFE.adcDacSync(0)





# error with library of DSA
#AFE.DSA.setRxDsa(0,24)
#AFE.DSA.setRxDsa(1,24)
#AFE.DSA.setRxDsa(2,24)
#AFE.DSA.setRxDsa(3,24)	
#CAFE.setRxDsa(0,1,10)

#  
#CAFE.setRxDsaMode(0,0,3)
#CAFE.setRxDsaMode(0,1,3)
#CAFE.setRxDsa(0,1,10)
#CAFE.setRxDsa(0,1,10)

Thanks,

Soumya

0 Camilo Garcia Trujillo over 1 year ago in reply to Soumya Mishra

TI__Expert 5055 points

Hi Soumya,

We will test this configuration on our side.

In the mean time, could you read registers 0xf0 through 0xf7 after the read check fail on line 10247 and provide us with the values?

These registers are the macro status registers and can provide us with information on why it is failing the Macro.

Also, just to make sure, you have the limits on your power supply for the EVM set to 5.5V and 5A correct?

Best,

Camilo

0 Soumya Mishra over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 50 points

Hi Camilo,

We have read the registers after and before index 10247.

Reading after the index:

- 0XF0 to 0xF4 read value is 0xFF

- 0XF5 to 0xF7 read value is 0x00

Reading before the index:

a. Till 10198 index:

- 0XF0 read value is 0x07.

- 0XF1 to 0xF7 read value is 0x00

b. then after index 10213 we have added the registers to reset the Macro page and then access the macro page.

001800

001820

80f000

80f100

80f200

80f300

80f400

80f500

80f600

80f700

001800

--In sequence to above registers, we are reading (JESD ASYNC FIFO OFFSET REGISTER) 0x30,0x31 & 0x32 and then rewriting the same. we are reading the 0xF0 - 0xF7.

- 0XF0 to 0xF4 read value is 0xFF

- 0XF5 to 0xF7 read value is 0x00

-- So, we are not doing read and rewrite operation, we are directly writing 0x11 in 0x30,0x31 & 0x32 registers. then reading 0xF0-0XF7.

- 0XF0 read value is 0x07.

- 0XF1 to 0xF7 read value is 0x00

c. From the above exercise we are able to remove all the errors by resetting the macro page, and we are able to get the link between ADC and FPGA, and real data is also received properly.

d. Why resetting the page is required to clear the errors in macro page. Kindly give clarity on what we have understood.

And, the power supply is set to 5V, and Current limit max is 40Amp.

Regards,

Soumya

0 Camilo Garcia Trujillo over 1 year ago in reply to Soumya Mishra

TI__Expert 5055 points

Hi Soumya,

Just to confirm, so the only changes you made were instead of reading and writing to registers 0x30,0x31 & 0x32 you just wrote 0x11 to registers 0x30,0x31 & 0x32, then you read registers 0xf0 to 0xf7 from the Macro page, and now the Macro passes

Could you also provide the new log file of SPI transactions?

Best,

Camilo

0 Soumya Mishra over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 50 points

Hi Camilo,

Yes, instead of reading and writing. We are just writing 0x11.After that Macro passes.

New SPI Write script is attached for your reference.

Regards,

Soumya

SPI_Reg.txt

0 Camilo Garcia Trujillo over 1 year ago in reply to Soumya Mishra

TI__Expert 5055 points

Hi Soumya,

I have forwarded this to our software team so that they can advise.

Just to make sure, if you remove the reads for registers 0xf0 to 0xf7 between index 10205 and 10215 like I have done in the file below does the macro still pass?

SPI_Reg_Test_NoStatusRead.txt

Best,

Camilo

0 Soumya Mishra over 1 year ago in reply to Camilo Garcia Trujillo

Prodigy 50 points

Hi Camilo,

Yes, Macro passes for registers that you have shared with us.

Regards,

Soumya

0 Soumya Mishra over 1 year ago in reply to Soumya Mishra

Prodigy 50 points

Hi Camilo,

Can we have any update on this.

Regards,

Soumya

0 Camilo Garcia Trujillo over 1 year ago in reply to Soumya Mishra

TI__Expert 5055 points

Hi Soumya,

Our software team is still looking into this.

I will reach out again to ask for an update.

Best,

Camilo