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AFE7950EVM: 204C with FB

David Hendry
Prodigy 30 points
Part Number: AFE7950EVM
Other Parts Discussed in Thread: TSW14J58EVM

Using the TSW14J58EVM  DC182_A7 to connect to the AFE7950EVM DC135 REV A

External ~500 MHz clock into REF_CLK_LOW and ~1.5 GHz clock into LMK_CLK_IN

I can get all Tx, Rx and FB ports working using 204B with the following script:

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels
#In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = False # setup FPGA (TSW14J58) using HSDC Pro 

##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]			#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
sysParams.ddcFactorFb	=	[6,6]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[24,24,24,24]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [1,1]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["22210","22210"]

sysParams.rxJesdTxScr	= [True,True,True,True]
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= False	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= False #True
lmkParams.inputClk		= 1474.56 #1500.0 #983.04 # Valid only when lmkParams.pllEn = False
#lmkParams.sysrefFreq	= 7.68 #3000/1024
lmkParams.lmkFrefClk	= False #True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56


##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)	# bit-wise; 4R,2F,4T

When I change to 204C, I can get Tx and Rx working but not the FB ports. I've tried many variations of the script below, but no success with the FB ports. No data comes through on the FB ports, just a blank white screen. When I change sysParams.LMFSHdFb to 22210, I get errors:

'list' object has no attribute '__buffer__'

No values received from capture Device

##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 983.04M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 983.04M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 0 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

#sysParams.RRFMode		= 0 #5					# RRF 0: 4T4R2F FDD Mode

		#####	RX	#####
sysParams.ddcFactorRx	=	[6,6,6,6] #[3,3,3,3]				#DDC decimation factor for RX A, B, C and D
sysParams.rxNco0		= 	[[9500,9500],			#Band0, Band1 for RXA 
							[9500,9500],        	#Band0, Band1 for RXB 
							[9500,9500],        	#Band0, Band1 for RXC 
							[9500,9500]]        	#Band0, Band1 for RXD 

		#####	FB	#####
#sysParams.fbEnable		=	[True,True]
sysParams.ddcFactorFb	=	[6,6] #[3,3]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]					#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[12,12,12,12]			#DUC interpolation factor for TX A, B, C and D
sysParams.txNco0		= 	[[9500,9500],			#Band0, Band1 for TXA 
							[9500,9500],        	#Band0, Band1 for TXB 
							[9500,9500],        	#Band0, Band1 for TXC 
							[9500,9500]]        	#Band0, Band1 for TXD 


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [1,1] #[3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [2,2]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"] #["44210","44210","44210","44210"]
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["24410","24410"]

sysParams.rxJesdTxScr	= [False,False,False,False]
sysParams.fbJesdTxScr	= [False,False]

sysParams.rxJesdTxK		= [1,1,1,1]
sysParams.fbJesdTxK		= [1,1]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]

		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [2,2] # 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdTx		= ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [4, 4]
sysParams.jesdRxScr		= [False,False,False,False]
sysParams.jesdRxK		= [1,1,1,1]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack	= False	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= False
lmkParams.inputClk		= 1474.56 #983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= False
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,0,15)	# bit-wise; 4R,2F,4T

Can you please advise what settings I need to change in the second script to get FB ports working with 204C?

Thanks, David.

  • 0
    TI__Genius 17831 points

    Hi David,

    One thing that I noticed is that the FB TDD is not being set in your second script. The command AFE.TOP.overrideTdd is used to override the Rx/Fb/Tx TDD pins so that the inputs/outputs are enabled. 

    Can you try changing the last line to 'AFE.TOP.overrideTdd(15,3,15)' and see if this fixes your problem?

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Thanks David, your advice above did the trick.

    I have a new issue:

    We have been exploring using a lower frequency ref clock. When we start with 3.84*128 MHz, the system works fine. Without turning the system off, we can reduce down to 3.84*64 MHz and 3.84*32 MHz without issues.

    However, when we start at 3.84*32 MHz from system turn on, there is no output from the Tx and the Rx/FB have the "'list' object has no attribute '__buffer__'" problem.

    Are you able to replicate this, and perhaps suggest a workaround?

  • 0 in reply to David Hendry
    TI__Genius 17831 points

    Hi David,

    When changing the reference clock frequency to the AFE are you also changing the Fref parameter in the bringup script? I have tested using a Fref of 122.88MHz and saw no issue with capturing data.

    When changing the a Fref of 122.88 I updated the following parameter in the bringup script. sysParams.FRef = 122.88

    Also, when looking closer at your scripts I noticed that you the lmkFrefClk parameter set to 'False' which should be set to 'True' when the LMK will provide the clock to the AFE. In order to test your scripts this should be set to 'True'.

    If this is set to 'False' then the LMK will not provide a clock to the AFE and instead a clock would need to be provided to the AFE externally. 

    Regards,

    David Chaparro