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Original question:

AFE7906: Regarding AFE7906 Ramp test

AFE7906: AFE7906: Regarding AFE7906 Ramp test2

Suematsu Tatsuya
Prodigy 180 points
Part Number: AFE7906


>Could you check that you are getting the Bytes correctly from your IP core?

>We have see other IP cores where there was a need to swap the Bytes

 

The IP core uses JESD204C from AMD's Vivado Design Suite
Is there any precedent for this core to be subject to byte swapping?

Also, using 3stx/4stx/5stx/6stx output
Since it is transferred with LMFS=48410, the Ramp step size of each 4 lane is
I want it to be a different value.

for example
Lane1=3stx Increment 1 or 5
Lane2=4stx Increment 2 or 6
Lane3=5stx Increment 3 or 7
Lane4=6stx Increment 4 or 8

Is such a setting possible?

.

  • 0
    TI__Mastermind 18311 points

    Hi Tatsuya,

    Yes, this is one of the IP cores that we have seen swaps the order of the bytes. We have seen that the IP re-orders the bytes such that Data15:8 will show up first followed by Data7:0. 

    If you are using the ADC ramp test pattern and want to adjust the step size then I would recommend using the below functions. These function allows you to enable the ramp pattern and set the increment size.

    AFE.JESD.ADCJESD[0].adcRampTestPattern(0,1,0) #chNo, En, RampInc: RxA
AFE.JESD.ADCJESD[0].adcRampTestPattern(1,1,1) #chNo, En, RampInc: RxB
AFE.JESD.ADCJESD[1].adcRampTestPattern(0,1,2) #chNo, En, RampInc: RxC
AFE.JESD.ADCJESD[1].adcRampTestPattern(1,1,3) #chNo, En, RampInc: RxD

    Regards,

    David Chaparro