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AFE7903: How to use TI JESD204 IP 32-bit TX/RX_LANE DATA WIDTH

Sangcheol Lee
Prodigy 40 points
Part Number: AFE7903
Other Parts Discussed in Thread: AFE7900EVM,

Hello, 

We are testing AFE7900EVM board with Xilinx ZCU102 together,

using the design files that are included in 'ZCU102_AFE79xx_8b10b_10Gbps' folder in TI JESD204 IP reference designs.

We have tested TI-JESD204c-IP with TX/RX_LN_DATA_WIDTH = 64 mode successfully, now we want to change the data width to 32 bits

Followings are that we have changed

 

1. Change the  LANE DATA WIDTH value in jesd_link_parms.vh 

`undef RX_LANE_DATA_WIDTH
//`define RX_LANE_DATA_WIDTH 64
`define RX_LANE_DATA_WIDTH 32

`undef TX_LANE_DATA_WIDTH
//`define TX_LANE_DATA_WIDTH 64
`define TX_LANE_DATA_WIDTH 32

2. Change the output clock of sys_pll IP from 122.88MHz to 245.76MHz

3. Change clock frequency and user data widh in transcevier ip 

After then we tried to generate FPGA bitstrem , but it stopped with 'write_bitstream ERROR' like below picture shown.  

Is there anything we missed to use 32-bit lane data width?


We are really appreciate any comments regarding this issue.

Thank you in advance.

-- Sangcheol

  • 0
    TI__Expert 5045 points

    Hi Sangcheol,

    We are looking into this and we will get back to you with an answer next week.

    Regards, 

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 40 points

    Hi Camilo,


    Thank you for your reply.
    There are two more things that we didn't describe in the previous question.

    ....

    4. Change the IP_TYPE

    We have changed IP_TYPE in "jesd_link_params.vh"
    becasue we are going to use only RX interface of AFE7903 in our custom design.

    //`define IP_TYPE "RXTX"
    `define IP_TYPE "RX"

    5. Change the original "refdesign_rx.sv"

    To support 32-bit data lane,
    we needed to change some part of your "refdesign_rx.sv" file properly.
    The Synthesis and Implemenation process in Vivado was successfuly completed,
    therefore we think the modification have no error.

    we are looking forward to hearing your answer soon.


    Regards,


    -- Sangcheol

  • 0 in reply to Sangcheol Lee
    TI__Genius 17891 points

    Hi Sangcheol,

    Can you confirm that in the Physical Resources tab of the Transceiver wizard you have selected the eight lanes that you are expecting data on? 

    When making changes to the reference design did you make any changes to the TI_204C_ref file?

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 40 points

    Hi David, 

    We did not change anythings in TI_204C_ref file and the eight lanes in transceiver still are on as shown in below figure.

    Regards, 

    -- Sangcheol

  • 0 in reply to Sangcheol Lee
    TI__Genius 17891 points

    Hi Sangcheol,

    I think there are two things that can be tested. The first is to assign these pins to the same quad that is being used for the receive lanes. The other is to comment out the pins, dac_lane, from the top level file, as they are not being used in the Rx only design. 

    Regards,

    David Chaparro