AFE7950: Problem converting a working design from 4 lane 64b/66b to 8b/10b

'''

'''
setupParams.skipFpga 				= 1
sysParams							= AFE.systemParams	
setupParams.fpgaRefClk 				= 122.88
AFE.systemStatus.loadTrims			= 1

sysParams.fbEnable = [False]*2
sysParams.FRef                    	= 245.76
sysParams.FadcRx                  	= 2457.6
sysParams.FadcFb				  	= 2457.6
sysParams.Fdac                    	= 2457.6*4
#sysParams.FadcRx                  	= 2500.0
#sysParams.FadcFb				  	= 2500.0
#sysParams.Fdac                    	= 2500.0*4

sysParams.enableDacInterleavedMode	= False  #DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx                	=['48410', '48410', '48410', '48410']	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["22210","22210"]

sysParams.LMFSHdTx                	= ["48410","48410","48410","48410"]

sysParams.jesdTxProtocol            = [0,0]    #8b/10b
sysParams.jesdRxProtocol            = [0,0]    #8b/10b
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux				= [0,1,2,3,4,5,6,7]	
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd					= [4, 4]

# scrambler is disabled
sysParams.rxJesdTxScr				= [True]*4
sysParams.fbJesdTxScr				= [True]*2
sysParams.jesdRxScr					= [True]*4




sysParams.rxJesdTxK					= [16]*4
sysParams.fbJesdTxK					= [16]*2
sysParams.jesdRxK				    = [16]*4

	
sysParams.ncoFreqMode 				= "1KHz"

sysParams.txNco0					= 	[[3441,3441],		#Band0, Band1 for TxA for NCO0
										[3441,3441],        #Band0, Band1 for TxB for NCO0
										[3441,3441],        #Band0, Band1 for TxC for NCO0
										[3441,3441]]        #Band0, Band1 for TxD for NCO0

sysParams.rxNco0					= 	[[3441,3441],		#Band0, Band1 for RxA for NCO0
										[3441,3441],        #Band0, Band1 for RxB for NCO0
										[3441,3441],        #Band0, Band1 for RxC for NCO0
										[3441,3441]]        #Band0, Band1 for RxD for NCO0
sysParams.fbNco0					= 	[1500,1800]			#FBA, FBC for NCO0

sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

sysParams.ddcFactorRx             	= [10]*4	# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [10]*2
sysParams.ducFactorTx             	= [40]*4

AFE.systemStatus.loadTrims			=1

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.xtalFreq                  =   122.88
#lmkParams.lmkVcoFreq                =   2457.6
lmkParams.lmkVcoFreq                =   2949.12

#lmkParams.xtalFreq                  =   156.25
#lmkParams.lmkVcoFreq                =   2500.0

lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat				= 0x00
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 0
sysParams.jesdCDLvdsSync			= 0
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True


# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'ADC_SYNC1',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'DAC_SYNC0',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
		

## Initiates LMK04828 and AFE79xx Bring-up
#lmk.logClassInst=logDumpInst
setupParams.skipLmk	=	False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
AFE.LMK.lmkConfig()

`default_nettype none
`timescale 1ps/1ps

// This is the top level module that contains the control
// and data path for each lane
//
module mgt_8b10b_wrap
#(
	parameter IP_ID = 0,
	parameter GT_TYPE = "GTHP",
	parameter NUM_LANES = 4,
	parameter NUM_QUADS = 1,
	parameter NUM_REFCLK_BUFFERS = 1,
	parameter TX_BYTES_PER_LANE = 8,
	parameter RX_BYTES_PER_LANE = 8,
	parameter GT_USERIO_IN_WIDTH = 16,
	parameter GT_USERIO_OUT_WIDTH = 16
)
(
	// Reference and free-run clock signals
	input wire	[NUM_REFCLK_BUFFERS-1:0] gt_refclk_p,
	input wire	[NUM_REFCLK_BUFFERS-1:0] gt_refclk_n,
	input wire	gt_reset_clk_freerun,

	// xcvr IP ports. Each Lane has one Tx and one
	// Rx data port. Leave unused ports unconnected
	// or tied off 
	input wire	[NUM_LANES-1:0] gt_rxp,
	input wire	[NUM_LANES-1:0] gt_rxn,
	input wire	[NUM_LANES-1:0] gt_rxpolarity,
	output wire	[NUM_LANES-1:0] gt_txp,
	output wire	[NUM_LANES-1:0] gt_txn,
	input wire	[NUM_LANES-1:0] gt_txpolarity,

	// Clock and CDR related output wires
	output wire	[NUM_QUADS-1:0] qpll0_locked,
	output wire	[NUM_QUADS-1:0] qpll1_locked,
	output wire	[NUM_LANES-1:0] cpll_locked,
	output wire	[NUM_LANES-1:0] cdr_locked,

	// Datapath related signals
	// These are controlled/used by the JESD Rx IP
	output wire	xcvr_rx_usrclk,
	output wire	xcvr_rx_usrclk2,
	output wire	xcvr_tx_usrclk,
	output wire	xcvr_tx_usrclk2,
	input wire	xcvr_reset_all,
	input wire	xcvr_reset_tx,
	input wire	xcvr_reset_rx,
	output wire	xcvr_reset_rx_done,
	output wire	xcvr_reset_tx_done,

	output wire [RX_BYTES_PER_LANE*8-1:0] xcvr_rx_data [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_is_comma [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_is_char [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_notintable [NUM_LANES-1:0],
	output wire [RX_BYTES_PER_LANE-1:0] xcvr_rx_disperror [NUM_LANES-1:0],
	input wire [NUM_LANES-1:0] xcvr_comma_det_align_en,
	output wire [NUM_LANES-1:0] xcvr_rx_byte_aligned,
	output wire [NUM_LANES-1:0] xcvr_rx_byte_realigned,

	input wire [TX_BYTES_PER_LANE*8-1:0] xcvr_tx_data [NUM_LANES-1:0],
	input wire [TX_BYTES_PER_LANE-1:0] xcvr_tx_data_is_char [NUM_LANES-1:0],
	input wire [GT_USERIO_IN_WIDTH-1:0] mgt_gpio_in,
	output wire [GT_USERIO_OUT_WIDTH-1:0] mgt_gpio_out

);

	wire [NUM_REFCLK_BUFFERS-1:0] gt_refclk0_buf;

genvar j;
generate for (j=0; j<NUM_REFCLK_BUFFERS; j=j+1)
begin

 if (GT_TYPE == "GTHP")
 begin

  IBUFDS_GTE4 #(
    .REFCLK_EN_TX_PATH  (1'b0),
    .REFCLK_HROW_CK_SEL (2'b00),
    .REFCLK_ICNTL_RX    (2'b00)
  ) IBUFDS_GTE4_INST (
    .I     (gt_refclk_p[j]),
    .IB     (gt_refclk_n[j]),
    .CEB   (1'b0),
    .O     (gt_refclk0_buf[j]),
    .ODIV2 ()
  );

 end

 else
 begin

  IBUFDS_GTE3 #(
    .REFCLK_EN_TX_PATH  (1'b0),
    .REFCLK_HROW_CK_SEL (2'b00),
    .REFCLK_ICNTL_RX    (2'b00)
  ) IBUFDS_GTE3_INST (
    .I     (gt_refclk_p[j]),
    .IB     (gt_refclk_n[j]),
    .CEB   (1'b0),
    .O     (gt_refclk0_buf[j]),
    .ODIV2 ()
  );

 end

end
endgenerate

	wire xcvr_userclk_rx_reset;
	wire xcvr_userclk_tx_reset;
	wire xcvr_userclk_rx_usrclk2;
	wire xcvr_userclk_rx_active;
	wire [NUM_LANES*RX_BYTES_PER_LANE*8-1:0] xcvr_userdata_rx;
	wire [NUM_LANES*16-1:0] xcvr_rxctrl0;
	wire [NUM_LANES*16-1:0] xcvr_rxctrl1;
	wire [NUM_LANES*8-1:0] xcvr_rxctrl2;
	wire [NUM_LANES*TX_BYTES_PER_LANE*8-1:0] xcvr_userdata_tx;
	wire [NUM_LANES*16-1:0] xcvr_txctrl0;
	wire [NUM_LANES*16-1:0] xcvr_txctrl1;
	wire [NUM_LANES*8-1:0] xcvr_txctrl2;
	wire [NUM_LANES*8-1:0] xcvr_rxctrl3;
	wire [NUM_LANES-1:0] xcvr_txpmaresetdone;
	wire [NUM_LANES-1:0] xcvr_rxpmaresetdone;

assign xcvr_userclk_rx_reset =
	~(&xcvr_rxpmaresetdone);

assign xcvr_userclk_tx_reset =
	~(&xcvr_txpmaresetdone);

genvar i;
generate for (i = 0; i < NUM_LANES; i=i+1)
begin : lane_gen

  assign xcvr_rx_data[i] = 
           xcvr_userdata_rx[RX_BYTES_PER_LANE*8*i +: RX_BYTES_PER_LANE*8];

  assign xcvr_rx_is_comma[i] = 
           xcvr_rxctrl2[8*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_is_char[i] = 
           xcvr_rxctrl0[16*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_notintable[i] = 
           xcvr_rxctrl3[8*i +: RX_BYTES_PER_LANE];

  assign xcvr_rx_disperror[i] = 
           xcvr_rxctrl1[16*i +: RX_BYTES_PER_LANE];

  assign xcvr_userdata_tx[TX_BYTES_PER_LANE*8*i +: TX_BYTES_PER_LANE*8] = 
     xcvr_tx_data[i];
           

  assign xcvr_txctrl2[8*i +: TX_BYTES_PER_LANE] = xcvr_tx_data_is_char[i];
           
end
endgenerate

  assign xcvr_txctrl1 = 'd0;
  assign xcvr_txctrl0 = 'd0;


generate
begin : xcvr_gen

if (TX_BYTES_PER_LANE == 8 && RX_BYTES_PER_LANE == 8)
gth_8b10b_xcvr xcvr_inst
(
	.gtwiz_userclk_tx_reset_in (xcvr_userclk_tx_reset),
	.gtwiz_userclk_tx_srcclk_out (),
	.gtwiz_userclk_tx_usrclk_out (xcvr_tx_usrclk),
	.gtwiz_userclk_tx_usrclk2_out (xcvr_tx_usrclk2),
	.gtwiz_userclk_tx_active_out (),
	.gtwiz_userclk_rx_reset_in (xcvr_userclk_rx_reset),
	.gtwiz_userclk_rx_srcclk_out (),
	.gtwiz_userclk_rx_usrclk_out (xcvr_rx_usrclk),
	.gtwiz_userclk_rx_usrclk2_out (xcvr_rx_usrclk2),
	.gtwiz_userclk_rx_active_out (),
	.gtwiz_reset_clk_freerun_in (gt_reset_clk_freerun),
	.gtwiz_reset_all_in (xcvr_reset_all),
	.gtwiz_reset_tx_pll_and_datapath_in (1'b0),
	.gtwiz_reset_tx_datapath_in (xcvr_reset_tx),
	//.gtwiz_reset_tx_datapath_in (mgt_gpio_in[1]),
	.gtwiz_reset_rx_pll_and_datapath_in (1'b0),
	.gtwiz_reset_rx_datapath_in (xcvr_reset_rx),
	//.gtwiz_reset_rx_datapath_in (mgt_gpio_in[1'b0]),
	.gtwiz_reset_rx_cdr_stable_out (),
	.gtwiz_reset_tx_done_out (xcvr_reset_tx_done),
	.gtwiz_reset_rx_done_out (xcvr_reset_rx_done),
	.gtwiz_userdata_tx_in (xcvr_userdata_tx),
	.gtwiz_userdata_rx_out (xcvr_userdata_rx),
	// MGTREFCLK0 of Quad 130 connected to REFCLK
	// inputs of both banks 130 and 129
	//.gtrefclk00_in ({2{gt_refclk0_buf}}),
	.gtrefclk00_in (gt_refclk0_buf),
	.gthrxn_in (gt_rxn),
	.gthrxp_in (gt_rxp),
	.qpll0lock_out (qpll0_locked),
	.qpll1lock_out (qpll1_locked),
	.cplllock_out (cpll_locked),
	.rxcdrlock_out (cdr_locked),
	.rx8b10ben_in ({NUM_LANES{1'b1}}),
	.rxcommadeten_in ({NUM_LANES{1'b1}}),
	.rxmcommaalignen_in (xcvr_comma_det_align_en),
	.rxpcommaalignen_in (xcvr_comma_det_align_en),
	.rxpolarity_in (gt_rxpolarity),
	.txpolarity_in (gt_txpolarity),
	.tx8b10ben_in ({NUM_LANES{1'b1}}),
	.txctrl0_in (xcvr_txctrl0),
	.txctrl1_in (xcvr_txctrl1),
	.txctrl2_in (xcvr_txctrl2),
	.gthtxn_out (gt_txn),
	.gthtxp_out (gt_txp),
	.gtpowergood_out (),
	.rxbyteisaligned_out (xcvr_rx_byte_aligned),
	.rxbyterealign_out (xcvr_rx_byte_realigned),
	.rxcommadet_out (),
	.rxctrl0_out (xcvr_rxctrl0),
	.rxctrl1_out (xcvr_rxctrl1),
	.rxctrl2_out (xcvr_rxctrl2),
	.rxctrl3_out (xcvr_rxctrl3),
	.rxpmaresetdone_out (xcvr_rxpmaresetdone),
	.txpmaresetdone_out (xcvr_txpmaresetdone)
);

end
endgenerate

assign mgt_gpio_out = {GT_USERIO_OUT_WIDTH{1'b0}};

endmodule
`default_nettype wire

// The following parameter defines if the 
// IP is in 8b/10b mode or 64b/66b mode
// Leave the second line commented if it is
// in 64b/66b, else uncomment it to enable 8b/10b
`undef IP_8B10B
`undef IP_64B66B
`define IP_8B10B
//`define IP_64B66B

`undef IP_TYPE
`define IP_TYPE "RXTX"

`undef ADC_RESOLUTION
`define ADC_RESOLUTION 16

`undef DAC_RESOLUTION
`define DAC_RESOLUTION 16
/////////////////////////////////////////////////
// The following parameters configure the JESD IP
// to interact with the transceiver created using
// the Vivado Transceiver wizard.
// Please ensure that the settings/parameters match
// that of the transceiver
/////////////////////////////////////////////////

// Set the number of lanes in the link
// This is equal to the number of lanes/channels
// in the transceiver IP
`undef NUMBER_OF_RX_LANES
`undef NUMBER_OF_TX_LANES

`define NUMBER_OF_RX_LANES 4
`define NUMBER_OF_TX_LANES 4

// Set the number of quads used in the transceiver
// IP. This is based on the transceiver Quad/Lane
// mapping. In this case, the 8 lanes are spread over
// 2 Quads
`undef NUMBER_OF_QUADS
`define NUMBER_OF_QUADS 1

// Select the type of Transceiver used in the IP
// Options are: GTH, GTP, GTX and GTY. Refer to
// the IP user guide for more details
// GTH : Ultrascale GTH
// GTHP : Ultrascale+ GTH
// GTY : Ultrascale GTY
// GTYP : Ultrascale+ GTY
// GTX : GTX in Zynq/Virtex/Kintex 7000 series
// GTP : GTP in Artix 7000 series
`undef MGT_TYPE
`define MGT_TYPE "GTHP"

// Set the number of Reference Clock
// Buffers used by the Transceiver
// In most cases, there is one clock per
// link, and the clock is internally routed
// to the individual Quad/Channel clocking logic
`undef NUMBER_OF_REFCLK_BUFFERS
`define NUMBER_OF_REFCLK_BUFFERS 1

// The following parameter controls the mapping
// of the ADC lanes to the transceiver lanes
// This helps account for any lane mapping mismatches
// on account of the board routing
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// For example a value of {3,1,0,2} will mean the 
// following:
//   1> Lane 0 of ADC is mapped to Lane 2 of the transceiver
//   2> Lane 1 of ADC is mapped to Lane 0 of the transceiver
//   3> Lane 2 of ADC is mapped to Lane 1 of the transceiver
//   4> Lane 3 of ADC is mapped to Lane 3 of the transceiver
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef LANE_ADC_TO_GT_MAP
//`define LANE_ADC_TO_GT_MAP {5,4,6,7,3,0,2,1}
`define LANE_ADC_TO_GT_MAP {3,0,2,1}

`undef LANE_DAC_TO_GT_MAP
//`define LANE_DAC_TO_GT_MAP {4,5,6,7,3,0,2,1}
`define LANE_DAC_TO_GT_MAP {3,0,2,1}

// The following parameter controls the polarity
// of the transceiver lanes. If the P and N differential
// pins are inverted between the transmitter and receiver,
// set the corresponding bit to '1'. If there is no inversion
// set the corresponding bit to 0.
// This parameter is from the perspective of the ADC
// and is ordered as {LANE_N,...,LANE2,LANE1,LANE0}
// NOTE: Ensure that the parameter below has as many bits
// as the number of lanes on the transceiver
`undef RX_LANE_POLARITY
//`define RX_LANE_POLARITY 8'b00110011
`define RX_LANE_POLARITY 4'b0011

`undef TX_LANE_POLARITY
//`define TX_LANE_POLARITY 8'b00001111
`define TX_LANE_POLARITY 4'b1111

// Set the width of the final lane data bus exported
// by each lane of the Rx IP.
`undef RX_LANE_DATA_WIDTH
`define RX_LANE_DATA_WIDTH 64

// Set the width of the final lane data bus exported
// by each lane of the Tx IP.
`undef TX_LANE_DATA_WIDTH
`define TX_LANE_DATA_WIDTH 64

// End of parameters related to the transceiver
//////////////////////////////////////////////

//////////////////////////////////////////////
// The rest of the parameters configure the IP
// for the correct operation of the 8b/10b data
// link protocol
// PLEASE NOTE: The parameters MUST be set based
// on those of the transmitting device, without
// which the link will not work or may display
// intermittent failures
//////////////////////////////////////////////

// The following parameter sets the value
// of the F (octets per frame) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_F_VAL
`define RX_F_VAL 4

`undef TX_F_VAL
`define TX_F_VAL 4

// The following parameter sets the value
// of the K (frames per multiframe) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
`undef RX_K_VAL
`define RX_K_VAL 16

`undef TX_K_VAL
`define TX_K_VAL 16

// End of parameters related to 8b/10b 
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// Parameter related to 64b/66b Encoding
// The following parameter sets the value
// of the E (multiblocks per extended multiblock) parameter of
// the device. Refer to the device datasheet
// for the values allowed. 
// This parameter is ignored if 8b/10b is chosen
`undef RX_E_VAL
`define RX_E_VAL 1

`undef TX_E_VAL
`define TX_E_VAL 1
///////////////////////////////////////////////////////////

`undef RBD_COUNT_WIDTH
`define RBD_COUNT_WIDTH 10

// End of parameters related to deterministic latency
///////////////////////////////////////////////////////////

///////////////////////////////////////////////////////////
// The following parameters are for the RX and TX BUFFERs
///////////////////////////////////////////////////////////
`undef RX_BUFFER
`define RX_BUFFER "NORM"

`undef BUFFER_RATIO
`define BUFFER_RATIO 1

`undef TX_BUFFER
`define TX_BUFFER "NORM"

///////////////////////////////////////////////////////////
// Define if the SYSREF is generated on the FPGA
///////////////////////////////////////////////////////////
//`undef SYSREF_GEN
//`define SYSREF_GEN

//`undef SYSREF_TARGET_COUNT
//`define SYSREF_TARGET_COUNT 8

// This reference design implements a
// TX/RX link of parameters LMFS = 4841
// L (number of lanes) = 4
// M (number of converters) = 8
// F (octets per frame) = 4
// S (samples per converter per frame) = 1

// Encoding protocol = 8b/10b
// K (frames per multi-frame) = 16

`default_nettype none
`timescale 1ps/1ps

`include "jesd_link_params.vh"

module TI_204c_IP_ref
#(
	parameter NUM_REFCLK_BUFFERS = `NUMBER_OF_REFCLK_BUFFERS,
	parameter NUM_RX_LANES = `NUMBER_OF_RX_LANES,
	parameter NUM_TX_LANES = `NUMBER_OF_TX_LANES
)
(
	// Signals related to the clock chip
	// Implemented if the FPGA is emulating the
	// clock chip (used with loopback cards)
	//`ifdef SYSREF_GEN
	//output wire	cc_sysref_out_p,
	//output wire	cc_sysref_out_n,
	//`endif

	// Signals related to the JESD IPs
	input wire	sys_clk_p,
	input wire	sys_clk_n,

	// Reference clock for the FPGA transceivers
	input wire	[NUM_REFCLK_BUFFERS-1:0] refclk_p,
	input wire	[NUM_REFCLK_BUFFERS-1:0] refclk_n,
	
	// Sysref for the JESD IP
	input wire	sysref_p,
	input wire	sysref_n,
	
	// SYNCn signals for 8b/10b link
	// initialization
	// These are defined only in 8b/10b mode
	`ifdef IP_8B10B
	output wire	adc_rx_sync_n,
	input wire	dac_tx_sync_n,
	`endif

	input wire	[NUM_RX_LANES-1:0] adc_lane_rxp,
	input wire	[NUM_RX_LANES-1:0] adc_lane_rxn,
	output wire	[NUM_TX_LANES-1:0] dac_lane_txp,
	output wire	[NUM_TX_LANES-1:0] dac_lane_txn
);

localparam IP_TYPE = `IP_TYPE;

`ifdef IP_8B10B
  localparam IP_PROTOCOL = 810;
`elsif IP_64B66B
  localparam IP_PROTOCOL = 6466;
`endif


// Resolutions of the converter
localparam ADC_RES = `ADC_RESOLUTION;
localparam DAC_RES = `DAC_RESOLUTION;

`ifdef IP_8B10B
// 8B/10B protocol related parameters
// for receiver
// Note: The value of F*K must be equal to or 
// an integral multiple of GT_RX_DATA_WIDTH
localparam PARAM_RX_F = `RX_F_VAL;
localparam PARAM_RX_K = `RX_K_VAL;
localparam PARAM_RX_HD = 0;

// 8B/10B protocol related PARAMeters
// for transmitter. These are left at default
// values if the IP is in 64b/66b mode
localparam PARAM_TX_N = `DAC_RESOLUTION;
localparam PARAM_TX_NPR = `DAC_RESOLUTION;
localparam PARAM_TX_CS = 0;
localparam PARAM_TX_F = `TX_F_VAL;
localparam PARAM_TX_K = `TX_K_VAL;
localparam PARAM_TX_DEVID = 0;
localparam PARAM_TX_BANKID = 0;
localparam PARAM_TX_HD = 0;
localparam PARAM_TX_M = 4;
localparam PARAM_TX_S = 1;
`endif

`ifdef IP_64B66B
// 64b/66b protocol related parameters
// for receiver
localparam PARAM_RX_E = `RX_E_VAL;

// 64b/66b protocol related parameters
// for transmitter
localparam PARAM_TX_E = `TX_E_VAL;
`endif

// MGT Transcevier related parameters
localparam GT_TYPE = `MGT_TYPE;
localparam NUM_QUADS = `NUMBER_OF_QUADS;

// Infer the lane index width from the number of lanes
localparam RX_LN_IDX_WIDTH = 
  (NUM_RX_LANES <= 2)? 1 :
  (NUM_RX_LANES <= 4)? 2 :
  (NUM_RX_LANES <= 8)? 3 :
  4;

localparam RX_LN_DATA_WIDTH = `RX_LANE_DATA_WIDTH;

localparam TX_LN_IDX_WIDTH = 
  (NUM_TX_LANES <= 2)? 1 :
  (NUM_TX_LANES <= 4)? 2 :
  (NUM_TX_LANES <= 8)? 3 :
  4;

localparam TX_LN_DATA_WIDTH = `TX_LANE_DATA_WIDTH;

localparam GT_USERIO_IN_WIDTH = 16;
localparam GT_USERIO_OUT_WIDTH = 16;

// Deterministic latency related parameters
// These are left at default (auto-computed by
// the RX IP)
localparam RX_RBD_COUNT_WIDTH = 10;
/*
localparam RX_SYSREF_OFFSET = 0;
localparam TX_SYSREF_OFFSET = 0;
localparam RX_LMFC_TARGET_COUNT = `LMFC_COUNT_VAL;
localparam RX_LEMC_TARGET_COUNT = `LEMC_COUNT_VAL;
*/

// Rx/Tx Buffer type control
localparam RX_BUFFER_TYPE = `RX_BUFFER;
localparam TX_BUFFER_TYPE = `TX_BUFFER;
localparam RX_BUFFER_RATIO = `BUFFER_RATIO;

///////////////////////////////////////
// Common reset and MGT related ports for the IP
////////////////////////////////////////////
// Async master reset
wire	master_reset_n;

// Free running clock required by the transceiver
wire	mgt_freerun_clock;

// Pad inputs for the Transceiver reference clock
wire	[NUM_REFCLK_BUFFERS-1:0] mgt_refclk_p;
wire	[NUM_REFCLK_BUFFERS-1:0] mgt_refclk_n;

// User GP input to the transceiver
wire	[GT_USERIO_IN_WIDTH-1:0] mgt_gpio_in;
// User GP output from the transceiver
wire	[GT_USERIO_OUT_WIDTH-1:0] mgt_gpio_out;

// PLL locked status signals
wire	[NUM_QUADS-1:0] qpll0_locked;
wire	[NUM_QUADS-1:0] qpll1_locked;
wire	[NUM_QUADS-1:0] cpll_locked;

////////////////////////////////////////////
// Primary Receiver related ports. These are
// independent of the 8B10b / 64B66B protocol
////////////////////////////////////////////

// Pad inputs for the Transceiver Rx lanes
wire	[NUM_RX_LANES-1:0] mgt_lane_rxp;
wire	[NUM_RX_LANES-1:0] mgt_lane_rxn;
wire	[NUM_RX_LANES-1:0] cfg_rx_lane_polarity;

// RXUSRCLK2 extracted by the transceiver
(* dont_touch = "TRUE" *) wire	mgt_rx_usrclk2;

// Lane Mapping between ADC and Transceiver
// Note: This is defined with respect to the 
// ADC lanes
wire	[RX_LN_IDX_WIDTH-1:0] cfg_rx_lane_map [NUM_RX_LANES-1:0]; 

// Application/System Clock for the Rx
wire	rx_sys_clock;

// Application/System Synchronous Reset for the Rx
wire	rx_sync_reset;

// lane enable signals (usually tied to all 1's; 
// but can be used for individual lane checks)
wire	[NUM_RX_LANES-1:0] cfg_rx_lane_enable;

wire rx_all_lanes_locked;
wire rx_release_all_lanes;

// Lane data outputs. There is one output data
// bus per lane
wire	[RX_LN_DATA_WIDTH-1:0] rx_lane_data [NUM_RX_LANES-1:0];

// Data valid signal. This applies simultaneously
// to all lanes
wire	rx_lane_data_valid;

// Rx Lane Buffer overflow indicator
wire	[NUM_RX_LANES-1:0] rx_lane_buffer_overflow;

// The following are the lane sideband signals
// in 8B/10B mode

// SYNCn signal
wire	rx_sync_n;
// Control signal for RX de-scrambling.
wire	cfg_rx_scrambling_enabled;

wire	[111:0] rx_lane_configuration_data [NUM_RX_LANES-1:0];
wire	[RX_LN_DATA_WIDTH/8-1:0] rx_lane_start_of_frame [NUM_RX_LANES-1:0];
wire	[RX_LN_DATA_WIDTH/8-1:0] rx_lane_start_of_multiframe [NUM_RX_LANES-1:0];

// The following are the lane sideband signals
// in 64b/66b mode

wire	[NUM_RX_LANES-1:0] rx_lane_start_of_mblock;
wire	[NUM_RX_LANES-1:0] rx_lane_start_of_emblock;
wire	[NUM_RX_LANES-1:0] rx_lane_crc_error;

// This is the master clear signal for all
// the error counts exported by the IP
wire	[NUM_RX_LANES-1:0] rx_clr_all_err_count;

// The following signals are the error related
// counts for the 8b/10b protocol
wire	[3:0] rx_lane_invalid_somf_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_somf_err_count;
wire	[3:0] rx_lane_invalid_eomf_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eomf_err_count;
wire	[3:0] rx_lane_invalid_eof_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eof_err_count;
wire	[3:0] rx_lane_notintable_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_notintable_err_count;
wire	[3:0] rx_lane_disp_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_disp_err_count;

// The following signals are the error related
// counts for the 64b/66b protocol
wire	[3:0] rx_lane_invalid_header_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_header_err_count;
wire	[3:0] rx_lane_invalid_eomb_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eomb_err_count;
wire	[3:0] rx_lane_invalid_eoemb_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_invalid_eoemb_err_count;
wire	[3:0] rx_lane_crc_mismatch_err_count [NUM_RX_LANES-1:0];
wire	[NUM_RX_LANES-1:0] rx_lane_clr_crc_mismatch_err_count;

// Rx Sysref control and status signals
wire	rx_sysref;
wire	[3:0] rx_sysref_realign_count;
wire	rx_clr_sysref_realign_count;
wire	rx_lmfc_pulse;
wire	rx_lemc_pulse;

wire	cfg_rx_det_latency_en;
wire	[RX_RBD_COUNT_WIDTH-1:0] cfg_rx_buffer_release_delay;
wire	[RX_RBD_COUNT_WIDTH-1:0] rx_lmfc_to_buffer_release_delay;
wire	[RX_RBD_COUNT_WIDTH-1:0] rx_lemc_to_buffer_release_delay;

////////////////////////////////////////////
// Primary Transmitter related ports. These are
// independent of the 8B10b / 64B66B protocol
////////////////////////////////////////////

// Pad inputs for the Transceiver Rx lanes
wire	[NUM_TX_LANES-1:0] mgt_lane_txp;
wire	[NUM_TX_LANES-1:0] mgt_lane_txn;
wire	[NUM_TX_LANES-1:0] cfg_tx_lane_polarity;

// TXUSRCLK2 extracted by the transceiver
wire	mgt_tx_usrclk2;

// Lane Mapping between ADC and Transceiver
// Note: This is defined with respect to the 
// ADC lanes
wire	[TX_LN_IDX_WIDTH-1:0] cfg_tx_lane_map [NUM_TX_LANES-1:0]; 

// Application/System Clock for the Rx
wire	tx_sys_clock;

// Application/System Synchronous Reset for the Rx
wire	tx_sync_reset;

// lane enable signals (usually tied to all 1's; 
// but can be used for individual lane checks)
wire	[NUM_TX_LANES-1:0] cfg_tx_lane_enable;

// Lane data inputs. There is one input data
// bus per lane
wire	[TX_LN_DATA_WIDTH-1:0] tx_lane_data [NUM_TX_LANES-1:0];

// Data ready signal. This applies simultaneously
// to all lanes
wire	tx_lane_data_ready;

// The following are the lane sideband signals
// in 8B/10B mode

// SYNCn signal
wire	tx_sync_n;

// Control signal for TX scrambling.
wire	cfg_tx_scrambling_enabled;

// Control signal for forcing Tx to ILAS mode
wire	cfg_tx_ilas_test_mode;

wire	[TX_LN_DATA_WIDTH/8-1:0] tx_lane_start_of_frame;
wire	[TX_LN_DATA_WIDTH/8-1:0] tx_lane_start_of_multiframe;

// The following are the lane sideband signals
// in 64b/66b mode

wire	tx_lane_start_of_mblock;
wire	tx_lane_start_of_emblock;

// Rx Sysref control and status signals
wire	tx_sysref;
wire	tx_lmfc_pulse;
wire	tx_lemc_pulse;

wire	[3:0] tx_sysref_realign_count;
wire	tx_clr_sysref_realign_count;

wire	[255:0] testport1_in;
wire	[255:0] testport1_out;
wire	[255:0] testport2_in;
wire	[255:0] testport2_out;
wire	[1049:0] testport3_in;
wire	[1049:0] testport3_out;

////////////////////////////////////////////////////
// System PLL for generating the free-run clock
// This also generates the sys_clock for the Rx
// and Tx IPs
////////////////////////////////////////////////////

wire sys_clock;

sys_pll pll_inst (
    .clk_in1_p (sys_clk_p),
    .clk_in1_n (sys_clk_n),
    .locked (),
    .reset (0),
    .sys_clk (sys_clock),
    .freerun_clk (mgt_freerun_clock));

/////////////////////////////////////////////
// IP related wire assignments
/////////////////////////////////////////////
assign rx_sys_clock = sys_clock;
assign tx_sys_clock = sys_clock;

assign mgt_refclk_p = refclk_p;
assign mgt_refclk_n = refclk_n;

//assign mgt_gpio_in[0] = rx_sync_reset;
//assign mgt_gpio_in[1] = tx_sync_reset;

//assign mgt_gpio_in[15:2] = 14'd0;
assign mgt_gpio_in = 16'd0;

assign mgt_lane_rxp = adc_lane_rxp;
assign mgt_lane_rxn = adc_lane_rxn;

assign cfg_rx_lane_polarity = `RX_LANE_POLARITY;

assign cfg_rx_lane_map = `LANE_ADC_TO_GT_MAP;

assign cfg_rx_lane_enable = {NUM_RX_LANES{1'b1}};
assign cfg_tx_lane_enable = {NUM_TX_LANES{1'b1}};

assign cfg_rx_scrambling_enabled = 1'b1;
assign cfg_tx_scrambling_enabled = 1'b1;

assign rx_release_all_lanes = 1'b1;

assign rx_clr_all_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_somf_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eomf_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eof_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_notintable_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_disp_err_count = {NUM_RX_LANES{1'b0}};

assign rx_lane_clr_invalid_header_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eomb_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_invalid_eoemb_err_count = {NUM_RX_LANES{1'b0}};
assign rx_lane_clr_crc_mismatch_err_count = {NUM_RX_LANES{1'b0}};

// Derive sysref from top level

wire sysref;
IBUFDS sysref_ibuf (.I(sysref_p), .IB(sysref_n), .O(sysref));

assign rx_sysref = sysref;
assign tx_sysref = sysref;

// Enable deterministic latency
assign cfg_rx_det_latency_en = 1'b1;

assign rx_clr_sysref_realign_count = 1'b0;
assign tx_clr_sysref_realign_count = 1'b0;

assign dac_lane_txp = mgt_lane_txp;
assign dac_lane_txn = mgt_lane_txn;

assign cfg_tx_lane_polarity = `TX_LANE_POLARITY;
assign cfg_tx_lane_map = `LANE_DAC_TO_GT_MAP;

assign	cfg_tx_ilas_test_mode = 1'b0;

`ifdef IP_8B10B
assign adc_rx_sync_n = rx_sync_n;
assign tx_sync_n = dac_tx_sync_n;
`else
assign tx_sync_n = 1'b0;
`endif

assign testport1_in = 'd0;
assign testport2_in = 'd0;
assign testport3_in = 'd0;

/////////////////////////////////////////////
// Instantiate the IP
/////////////////////////////////////////////

TI_204c_IP
	#(
	// IP type and protocol
	// Allowed values are RX / TX / RXTX
	.IP_TYPE (IP_TYPE),
	.IP_PROTOCOL (IP_PROTOCOL),

	// Resolutions of the converter
	.ADC_RES (ADC_RES),
	.DAC_RES (DAC_RES),

	`ifdef IP_8B10B
	// 8B/10B protocol related parameters
	// for receiver
	// Note: The value of F*K must be equal to or 
	// an integral multiple of GT_RX_DATA_WIDTH
	.PARAM_RX_F (PARAM_RX_F),
	.PARAM_RX_K (PARAM_RX_K),
	.PARAM_RX_HD (PARAM_RX_HD),

	// 8B/10B protocol related PARAMeters
	// for transmitter
	.PARAM_TX_N (PARAM_TX_N),
	.PARAM_TX_NPR (PARAM_TX_NPR),
	.PARAM_TX_CS (PARAM_TX_CS),
	// Note: The value of F*K must be equal to or 
	// an integral multiple of GT_TX_DATA_WIDTH
	.PARAM_TX_F (PARAM_TX_F),
	.PARAM_TX_K (PARAM_TX_K),
	.PARAM_TX_DEVID (PARAM_TX_DEVID),
	.PARAM_TX_BANKID (PARAM_TX_BANKID),
	.PARAM_TX_HD (PARAM_TX_HD),
	.PARAM_TX_M (PARAM_TX_M),
	.PARAM_TX_S (PARAM_TX_S),
	`endif

	`ifdef IP_64B66B
	// 64b/66b protocol related parameters
	// for receiver
	.PARAM_RX_E (PARAM_RX_E),

	// 64b/66b protocol related parameters
	// for transmitter
	.PARAM_TX_E (PARAM_TX_E),
	`endif

	// MGT Transcevier related parameters
	.GT_TYPE (GT_TYPE),
	.NUM_REFCLK_BUFFERS (NUM_REFCLK_BUFFERS),
	.NUM_QUADS (NUM_QUADS),
	.NUM_RX_LANES (NUM_RX_LANES),
	.RX_LN_IDX_WIDTH (RX_LN_IDX_WIDTH),
	.RX_LN_DATA_WIDTH (RX_LN_DATA_WIDTH),
	.NUM_TX_LANES (NUM_TX_LANES),
	.TX_LN_IDX_WIDTH (TX_LN_IDX_WIDTH),
	.TX_LN_DATA_WIDTH (TX_LN_DATA_WIDTH),
	.GT_USERIO_IN_WIDTH (GT_USERIO_IN_WIDTH),
	.GT_USERIO_OUT_WIDTH (GT_USERIO_OUT_WIDTH),

	/*
	// Deterministic latency related parameters
	.RX_SYSREF_OFFSET (RX_SYSREF_OFFSET),
	.TX_SYSREF_OFFSET (TX_SYSREF_OFFSET),
	.RX_RBD_COUNT_WIDTH (RX_RBD_COUNT_WIDTH),
	.RX_LMFC_TARGET_COUNT (RX_LMFC_TARGET_COUNT),
	.RX_LEMC_TARGET_COUNT (RX_LEMC_TARGET_COUNT),
	*/

	// Rx/Tx Buffer type control
	.RX_BUFFER_TYPE (RX_BUFFER_TYPE),
	.TX_BUFFER_TYPE (TX_BUFFER_TYPE),
	.RX_BUFFER_RATIO (RX_BUFFER_RATIO)

	/*
	// Rx Transport layer related parameters
	.RX_TL_ENABLED (RX_TL_ENABLED),
	.TL_PARAM1 (TL_PARAM1),
	.TL_PARAM2 (TL_PARAM2),
	.TL_PARAM3 (TL_PARAM3),
	.SAMPLES_PER_CYCLE_PER_LANE (SAMPLES_PER_CYCLE_PER_LANE),
	.TL_TYPE (TL_TYPE)
	*/

)
TI_IP_inst	(
	////////////////////////////////////////////
	// Common reset and MGT related ports for the IP
	////////////////////////////////////////////
	// Async master reset
	.master_reset_n (master_reset_n),

	// Free running clock required by the transceiver
	.mgt_freerun_clock (mgt_freerun_clock),

	// Pad inputs for the Transceiver reference clock
	.mgt_refclk_p (mgt_refclk_p),
	.mgt_refclk_n (mgt_refclk_n),

	// User GP input to the transceiver
	.mgt_gpio_in (mgt_gpio_in),
	// User GP output from the transceiver
	.mgt_gpio_out (mgt_gpio_out),

	// PLL locked status signals
	.qpll0_locked (qpll0_locked),
	.qpll1_locked (qpll1_locked),
	.cpll_locked (cpll_locked),

	////////////////////////////////////////////
	// Primary Receiver related ports. These are
	// independent of the 8B10b / 64B66B protocol
	////////////////////////////////////////////

	// Pad inputs for the Transceiver Rx lanes
	.mgt_lane_rxp (mgt_lane_rxp),
	.mgt_lane_rxn (mgt_lane_rxn),
	.cfg_rx_lane_polarity (cfg_rx_lane_polarity),

	// RXUSRCLK2 extracted by the transceiver
	.mgt_rx_usrclk2 (mgt_rx_usrclk2),

	// Lane Mapping between ADC and Transceiver
	// Note: This is defined with respect to the 
	// ADC lanes
	.cfg_rx_lane_map (cfg_rx_lane_map), 

	// Application/System Clock for the Rx
	.rx_sys_clock (rx_sys_clock),

	// Application/System Synchronous Reset for the Rx
	.rx_sync_reset (rx_sync_reset),

	// lane enable signals (usually tied to all 1's, 
	// but can be used for individual lane checks)
	.cfg_rx_lane_enable (cfg_rx_lane_enable),

	// Lane release status and control
	.rx_all_lanes_locked (rx_all_lanes_locked),
	.rx_release_all_lanes (rx_release_all_lanes),

	// Lane data outputs. There is one output data
	// bus per lane
	.rx_lane_data (rx_lane_data),

	// Data valid signal. This applies simultaneously
	// to all lanes
	.rx_lane_data_valid (rx_lane_data_valid),

	// Rx Lane Buffer overflow indicator
	.rx_lane_buffer_overflow (rx_lane_buffer_overflow),

	// The following signals comprise the lane data
	// directly packed and sorted as samples. These are 
	// generated only if the transport layer is included 
	// inside the IP
	.rx_lane_samples (),
	.rx_lane_samples_valid (),

	// The following are the lane sideband signals
	// in 8B/10B mode

	// SYNCn signal
	.rx_sync_n (rx_sync_n),
	// Control signal for RX de-scrambling.
	.cfg_rx_scrambling_enabled (cfg_rx_scrambling_enabled),

	.rx_lane_configuration_data (rx_lane_configuration_data),
	.rx_lane_start_of_frame (rx_lane_start_of_frame),
	.rx_lane_start_of_multiframe (rx_lane_start_of_multiframe),

	// The following are the lane sideband signals
	// in 64b/66b mode

	.rx_lane_start_of_mblock (rx_lane_start_of_mblock),
	.rx_lane_start_of_emblock (rx_lane_start_of_emblock),
	.rx_lane_crc_error (rx_lane_crc_error),

	// This is the master clear signal for all
	// the error counts exported by the IP
	.rx_clr_all_err_count (rx_clr_all_err_count),

	// The following signals are the error related
	// counts for the 8b/10b protocol
	.rx_lane_invalid_somf_err_count (rx_lane_invalid_somf_err_count),
	.rx_lane_clr_invalid_somf_err_count (rx_lane_clr_invalid_somf_err_count),
	.rx_lane_invalid_eomf_err_count (rx_lane_invalid_eomf_err_count),
	.rx_lane_clr_invalid_eomf_err_count (rx_lane_clr_invalid_eomf_err_count),
	.rx_lane_invalid_eof_err_count (rx_lane_invalid_eof_err_count),
	.rx_lane_clr_invalid_eof_err_count (rx_lane_clr_invalid_eof_err_count),
	.rx_lane_notintable_err_count (rx_lane_notintable_err_count),
	.rx_lane_clr_notintable_err_count (rx_lane_clr_notintable_err_count),
	.rx_lane_disp_err_count (rx_lane_disp_err_count),
	.rx_lane_clr_disp_err_count (rx_lane_clr_disp_err_count),

	// The following signals are the error related
	// counts for the 64b/66b protocol
	.rx_lane_invalid_header_err_count (rx_lane_invalid_header_err_count),
	.rx_lane_clr_invalid_header_err_count (rx_lane_clr_invalid_header_err_count),
	.rx_lane_invalid_eomb_err_count (rx_lane_invalid_eomb_err_count),
	.rx_lane_clr_invalid_eomb_err_count (rx_lane_clr_invalid_eomb_err_count),
	.rx_lane_invalid_eoemb_err_count (rx_lane_invalid_eoemb_err_count),
	.rx_lane_clr_invalid_eoemb_err_count (rx_lane_clr_invalid_eoemb_err_count),
	.rx_lane_crc_mismatch_err_count (rx_lane_crc_mismatch_err_count),
	.rx_lane_clr_crc_mismatch_err_count (rx_lane_clr_crc_mismatch_err_count),

	// Rx Sysref control and status signals
	.rx_sysref (rx_sysref),
	.rx_sysref_realign_count (rx_sysref_realign_count),
	.rx_clr_sysref_realign_count (rx_clr_sysref_realign_count),
	.rx_lmfc_pulse (rx_lmfc_pulse),
	.rx_lemc_pulse (rx_lemc_pulse),

	.cfg_rx_det_latency_en (cfg_rx_det_latency_en),
	.cfg_rx_buffer_release_delay (cfg_rx_buffer_release_delay),
	.rx_lmfc_to_buffer_release_delay (rx_lmfc_to_buffer_release_delay),
	.rx_lemc_to_buffer_release_delay (rx_lemc_to_buffer_release_delay),

	////////////////////////////////////////////
	// Primary Transmitter related ports. These are
	// independent of the 8B10b / 64B66B protocol
	////////////////////////////////////////////

	// Pad inputs for the Transceiver Rx lanes
	.mgt_lane_txp (mgt_lane_txp),
	.mgt_lane_txn (mgt_lane_txn),
	.cfg_tx_lane_polarity (cfg_tx_lane_polarity),

	// TXUSRCLK2 extracted by the transceiver
	.mgt_tx_usrclk2 (mgt_tx_usrclk2),

	// Lane Mapping between ADC and Transceiver
	// Note: This is defined with respect to the 
	// ADC lanes
	.cfg_tx_lane_map (cfg_tx_lane_map), 

	// Application/System Clock for the Rx
	.tx_sys_clock (tx_sys_clock),

	// Application/System Synchronous Reset for the Rx
	.tx_sync_reset (tx_sync_reset),

	// lane enable signals (usually tied to all 1's, 
	// but can be used for individual lane checks)
	.cfg_tx_lane_enable (cfg_tx_lane_enable),

	// Lane data inputs. There is one input data
	// bus per lane
	.tx_lane_data (tx_lane_data),

	// Data ready signal. This applies simultaneously
	// to all lanes
	.tx_lane_data_ready (tx_lane_data_ready),

	// The following are the lane sideband signals
	// in 8B/10B mode

	// SYNCn signal
	.tx_sync_n (tx_sync_n),

	// Control signal for TX scrambling.
	.cfg_tx_scrambling_enabled (cfg_tx_scrambling_enabled),

	// Control signal for forcing Tx to ILAS mode
	.cfg_tx_ilas_test_mode (cfg_tx_ilas_test_mode),

	.tx_lane_start_of_frame (tx_lane_start_of_frame),
	.tx_lane_start_of_multiframe (tx_lane_start_of_multiframe),

	// The following are the lane sideband signals
	// in 64b/66b mode

	.tx_lane_start_of_mblock (tx_lane_start_of_mblock),
	.tx_lane_start_of_emblock (tx_lane_start_of_emblock),


	// Rx Sysref control and status signals
	.tx_sysref (tx_sysref),
	.tx_lmfc_pulse (tx_lmfc_pulse),
	.tx_lemc_pulse (tx_lemc_pulse),

	.tx_sysref_realign_count (tx_sysref_realign_count),
	.tx_clr_sysref_realign_count (tx_clr_sysref_realign_count),
	.testport1_in (testport1_in),
	.testport1_out (testport1_out),
	.testport2_in (testport2_in),
	.testport2_out (testport2_out),
	.testport3_in (testport3_in),
	.testport3_out (testport3_out)

);

////////////////////////////////////////////////////
// Instantiate the VIO module that will control
// the JESD IP's reset and misc signals
////////////////////////////////////////////////////
wire rx_sync_reset_vio;
wire tx_sync_reset_vio;
wire [1:0] sine_attenuation_factor;

vio vio_inst (
	.clk (mgt_freerun_clock),
	`ifdef IP_8B10B
	.probe_in0 (rx_lmfc_to_buffer_release_delay),
	`else
	.probe_in0 (rx_lemc_to_buffer_release_delay),
	`endif
	.probe_in1 (qpll0_locked),
	.probe_in2 (qpll1_locked),
	.probe_in3 (cpll_locked),
	.probe_out0 (master_reset_n),
	.probe_out1 (rx_sync_reset_vio),
	.probe_out2 (tx_sync_reset_vio),
	.probe_out3 (cfg_rx_buffer_release_delay)
	);

// Synchronize the Rx sync reset from VIO clock to rx_sys_clock
// Synchronize the Tx sync reset from VIO clock to tx_sys_clock
//
(* ASYNC_REG="true" *) reg [1:0] rx_sync_reset_sync;
(* ASYNC_REG="true" *) reg [1:0] tx_sync_reset_sync;

////////////////////////////////////////////////////
// Logic related to the Tx
// Instantiated only if the Tx mode exists
////////////////////////////////////////////////////

genvar i;
generate
begin : tx_refdesign_gen

if (IP_TYPE == "RXTX" || IP_TYPE == "TX")
begin

always @(posedge tx_sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  tx_sync_reset_sync <= 2'b11;
	 end
	else
	 begin
	  tx_sync_reset_sync[0] <= tx_sync_reset_vio;
	  tx_sync_reset_sync[1] <= tx_sync_reset_sync[0];
	 end
end

assign tx_sync_reset = tx_sync_reset_sync[1];

refdesign_tx
#(
	.IP_PROTOCOL (IP_PROTOCOL),
	.NUM_TX_LANES (NUM_TX_LANES),
	.TX_LN_DATA_WIDTH (TX_LN_DATA_WIDTH)
)
refdesign_tx_inst (
	.master_reset_n (master_reset_n),
	.mgt_freerun_clock (mgt_freerun_clock),
	.tx_sys_clock (tx_sys_clock),
	.tx_sync_reset (tx_sync_reset),
	.tx_lane_data (tx_lane_data),
	.tx_lane_data_ready (tx_lane_data_ready),
	.tx_sync_n (tx_sync_n),
	.tx_lane_start_of_frame (tx_lane_start_of_frame),
	.tx_lane_start_of_multiframe (tx_lane_start_of_multiframe),
	.tx_lane_start_of_mblock (tx_lane_start_of_mblock),
	.tx_lane_start_of_emblock (tx_lane_start_of_emblock),
	.tx_sysref (tx_sysref),
	.tx_lmfc_pulse (tx_lmfc_pulse),
	.tx_lemc_pulse (tx_lemc_pulse),
	.tx_sysref_realign_count (tx_sysref_realign_count),
	.tx_clr_sysref_realign_count (tx_clr_sysref_realign_count),
	.sine_att_factor (sine_attenuation_factor)
);

end
else
begin : tx_default_gen

// If Tx IP doesn't exist, drive tx_lane_data to 0's
for (i=0; i<NUM_TX_LANES; i=i+1)
  assign tx_lane_data[i] = {TX_LN_DATA_WIDTH{1'b0}};

assign tx_sync_reset = 1'b1;

end

end
endgenerate

////////////////////////////////////////////////////
// END Logic related to the Tx
////////////////////////////////////////////////////

////////////////////////////////////////////////////
// Logic related to the Rx
// Instantiated only if the Rx mode exists
////////////////////////////////////////////////////

if (IP_TYPE == "RXTX" || IP_TYPE == "RX")
begin : rx_refdesign_gen

always @(posedge rx_sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  rx_sync_reset_sync <= 2'b11;
	 end
	else
	 begin
	  rx_sync_reset_sync[0] <= rx_sync_reset_vio;
	  rx_sync_reset_sync[1] <= rx_sync_reset_sync[0];
	 end
end

assign rx_sync_reset = rx_sync_reset_sync[1];

refdesign_rx
#(
	.IP_PROTOCOL (IP_PROTOCOL),
	.NUM_RX_LANES (NUM_TX_LANES),
	.RX_LN_DATA_WIDTH (RX_LN_DATA_WIDTH),
	.ADC_RES (ADC_RES)
	)
refdesign_rx_inst (
	.mgt_freerun_clock (mgt_freerun_clock),
	.rx_sys_clock (rx_sys_clock),
	.rx_sync_reset (rx_sync_reset),
	.rx_all_lanes_locked (rx_all_lanes_locked),
	.rx_release_all_lanes (rx_release_all_lanes),
	.rx_lane_data (rx_lane_data),
	.rx_lane_data_valid (rx_lane_data_valid),
	.rx_lane_buffer_overflow (rx_lane_buffer_overflow),
	.rx_sync_n (rx_sync_n),
	.rx_lane_configuration_data (rx_lane_configuration_data),
	.rx_lane_start_of_frame (rx_lane_start_of_frame),
	.rx_lane_start_of_multiframe (rx_lane_start_of_multiframe),
	.rx_lane_start_of_mblock (rx_lane_start_of_mblock),
	.rx_lane_start_of_emblock (rx_lane_start_of_emblock),
	.rx_lane_crc_error (rx_lane_crc_error),
	.rx_lane_invalid_somf_err_count (rx_lane_invalid_somf_err_count),
	.rx_lane_invalid_eomf_err_count (rx_lane_invalid_eomf_err_count),
	.rx_lane_invalid_eof_err_count (rx_lane_invalid_eof_err_count),
	.rx_lane_notintable_err_count (rx_lane_notintable_err_count),
	.rx_lane_disp_err_count (rx_lane_disp_err_count),
	.rx_lane_invalid_header_err_count (rx_lane_invalid_header_err_count),
	.rx_lane_invalid_eomb_err_count (rx_lane_invalid_eomb_err_count),
	.rx_lane_invalid_eoemb_err_count (rx_lane_invalid_eoemb_err_count),
	.rx_lane_crc_mismatch_err_count (rx_lane_crc_mismatch_err_count),
	.rx_sysref (rx_sysref),
	.rx_sysref_realign_count (rx_sysref_realign_count),
	.rx_clr_sysref_realign_count (rx_clr_sysref_realign_count),
	.rx_lmfc_pulse (rx_lmfc_pulse),
	.rx_lemc_pulse (rx_lemc_pulse)
);

end
else
begin : rx_default_gen

assign rx_sync_reset = 1'b1;

end

////////////////////////////////////////////////////
// END Logic related to the Rx
////////////////////////////////////////////////////

////////////////////////////////////////////////////
// Instantiate the Emulated Clock Chip
////////////////////////////////////////////////////

`ifdef SYSREF_GEN

// Instantiate the SYSREF generation logic 
// The period is based on the SYSREF_TARGET_COUNT
// parameter

reg [7:0] sysref_count;
reg sysref_toggle;

always @(posedge sys_clock or negedge master_reset_n)
begin
	if (!master_reset_n)
	 begin
	  sysref_count = 'd0;
	  sysref_toggle <= 1'b0;
	 end
	else
	if (sysref_count == `SYSREF_TARGET_COUNT)
	 begin
	  sysref_count = 'd1;
	  sysref_toggle <= ~sysref_toggle;
	 end
	else
	 sysref_count <= sysref_count+1;
end

(* IOB_REG="true" *) reg sysref_final;

always @(posedge sys_clock)
  sysref_final <= sysref_toggle;

OBUFDS sysref_obuf (.I(sysref_final), 
  .O(cc_sysref_out_p), 
  .OB(cc_sysref_out_n));

`endif

endmodule
`default_nettype wire