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AFE7950: Spectrum and latte script

Part Number: AFE7950

Hi,

Could you check below weird spectrum?

Customer would like to use 1.5GHz interface rate on 1 Tx ch.

Center frequency is now 5GHz due to spectrum analyzer specification but they will use 9.6GHz finally.

Additional question is that AFE7950 use signed signal?

Below is latte script.

 

##############  Read me   ##############

#Select AFE7950 TX_44210; Data Rate = 1500M

#Select AFE7950 RX_22210; Data Rate = 1500M ---> To capture 1 RX channels

#Select AFE7950 FB_22210; Data Rate = 1500M ---> To capture 1 FB channels

 

sysParams=AFE.systemParams

sysParams.__init__();sysParams.chipVersion=chipVersion

 

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 

 

##############  Top Level   ##############

sysParams.FRef   = 250

sysParams.FadcRx  = 3000

sysParams.FadcFb  = 3000

sysParams.Fdac   = 12000

sysParams.RRFMode  = 5

             #RRFMode 0: 4T4R2F FDD Mode

             #RRFMode 1: 4T4R1F FDD Mode

             #RRFMode 2: 4T2R2F FDD Mode Quad Band

             #RRFMode 5: 4T4R2F TDD Non-Shared

             #RRFMode 6: 4T4R1F TDD Non-shared

             #RRFMode 7: 4T4R2F TDD Shared

             #RRFMode 8: 4T4R1F TDD Shared

             #RRFMode 10: 2T2R1F TDD AB / 2T2R1F FDD CD

             #RRFMode 11: 2T2R1F FDD AB / 2T2R1F TDD CD

sysParams.externalClockRx=False

sysParams.externalClockTx=False

             

##############  Digital Chain  ##############

 

  ##### RX #####

sysParams.ddcFactorRx = [2,2,2,2]    #DDC decimation factor for RX A, B, C and D. value = FadcRX/Data Rate

sysParams.numBandRx  = [0,0,0,0]    #RX A, B, C and D are single band.

sysParams.numRxNCO   = 1      #No NCO switching.

sysParams.ncoRxMode  = [0,0]

sysParams.rxNco0   [[5000,5000],   #Band0, Band1 for RXA. value = RF center frequency

       [5000,5000],         #Band0, Band1 for RXB. value = RF center frequency

       [5000,5000],         #Band0, Band1 for RXC. value = RF center frequency

       [5000,5000]]         #Band0, Band1 for RXD. value = RF center frequency

sysParams.rxEnable  = [True,True,False,False] #RXA enable

             #RXB enable

             #RXC disable

             #RXD disable

 

  ##### FB #####

sysParams.ddcFactorFb = [2,2]     #DDC decimation factor for FB 1 and 2. value = FadcFb/Data Rate

sysParams.numFbNCO    1      #No NCO switching.

sysParams.ncoFbMode  = 0

sysParams.fbNco0   [5000,5000]    #Band0 for FB1 and FB2. value = RF center frequency

sysParams.fbEnable  = [False,False]   #FB AB disable

             #FB CD disable

 

  ##### TX #####

sysParams.ducFactorTx = [8,8,8,8]    #DUC interpolation factor for TX A, B, C and D. value = Fdac/Data Rate

sysParams.numBandsTx = [0,0,0,0]    #TX A, B, C and D are single band.

sysParams.combineDucMode= [0,0]     #No combine the 2 TX channels.

sysParams.numTxNCO  = 1      #No NCO switching.

sysParams.ncoTxMode  = [0,0]

sysParams.txNco0   [[5000,5000],   #Band0, Band1 for TXA. value = RF center frequency

       [5000,5000],         #Band0, Band1 for TXB. value = RF center frequency

       [5000,5000],         #Band0, Band1 for TXC. value = RF center frequency

       [5000,5000]]         #Band0, Band1 for TXD. value = RF center frequency

sysParams.txEnable  = [True,True,False,False] #TXA enable

             #TXB enable

             #TXC disable

             #TXD disable

 

##############  JESD  ##############

 

  ##### ADC-JESD #####

sysParams.jesdSystemMode= [3,3]

             #SystemMode 0: 2R1F-FDD      ; rx1    -rx2    -fb     -fb

             #SystemMode 1: 1R1F-FDD      ; rx     -rx     -fb     -fb

             #SystemMode 2: 2R-FDD       ; rx1    -rx1    -rx2    -rx2

             #SystemMode 3: 1R        ; rx     -rx     -rx     -rx

             #SystemMode 4: 1F        ; fb     -fb     -fb     -fb

             #SystemMode 5: 1R1F-TDD      ; rx12/fb-rx12/fb-rx12/fb-rx12/fb

             #SystemMode 8: 1R1F-TDD 1R-FDD     ; rx1    -       -rx2/fb -rx2/fb

             

sysParams.jesdTxProtocol= [2,2]      # 0 - 8b/10b encoding; 2 - 64b/66b encoding 

sysParams.LMFSHdRx  = ["22210","22210","22210","22210"]

             # The 2nd and 4th are valid only for jesdSystemMode values in (0,2).

             # For other modes, select 4 converter modes for 1st and 3rd.

sysParams.LMFSHdFb  = ["22210","22210"]

 

sysParams.rxJesdTxScr = [False,False,False,False]

sysParams.fbJesdTxScr = [False,False]

 

sysParams.rxJesdTxK  = [1,1,1,1]     #LCM(256,F)/256 for JESD204C. 

sysParams.fbJesdTxK  = [1,1]

 

sysParams.jesdTxLaneMux = [1,0,2,3,4,5,6,7]   # Enter which lanes you want in each location. 

             # For example, if you want to exchange the first two lines of each 2T,

             #  this should be [[1,0,2,3],[5,4,6,7]]

 

  ##### DAC-JESD #####

sysParams.jesdRxProtocol= [2,2]      # 0 - 8b/10b encoding; 2 - 64b/66b encoding 

sysParams.LMFSHdTx  = ["44210","44210","44210","44210"]

sysParams.jesdRxLaneMux = [2,1,0,3,4,5,6,7]   # Enter which lanes you want in each location.

             # For example, if you want to exchange the first two lines of each 2R

             #  this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd  = [4, 4]

sysParams.jesdRxScr  = [False,False,False,False]

sysParams.jesdRxK  = [1,1,1,1]

 

  ##### JESD Common #####

 

sysParams.jesdABLvdsSync= True

sysParams.jesdCDLvdsSync= True

sysParams.syncLoopBack = False #JESD Sync signal is connected to FPGA

 

##############  GPIO  ##############

sysParams.gpioMapping = {

      'H8': 'ADC_SYNC0',

      'H7': 'ADC_SYNC1',

      'N8': 'ADC_SYNC2',

      'N7': 'ADC_SYNC3',

      'H9': 'DAC_SYNC0',

      'G9': 'DAC_SYNC1',

      'N9': 'DAC_SYNC2',

      'P9': 'DAC_SYNC3',

      'P14': 'GLOBAL_PDN',

      'K14': 'FBABTDD',

      'R6': 'FBCDTDD',

      'H15': ['TXATDD','TXBTDD'],

      'V5': ['TXCTDD','TXDTDD'],

      'E7': ['RXATDD','RXBTDD'],

      'R15': ['RXCTDD','RXDTDD']}

 

##############  LMK Params  ##############

lmkParams.pllEn   = True

lmkParams.inputClk  = 983.04 # Valid only when lmkParams.pllEn = False

lmkParams.lmkFrefClk = True

setupParams.fpgaRefClk  = 375

 

##############  Logging  ##############

logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")

logDumpInst.logFormat=0x1 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.

logDumpInst.rewriteFile=1

logDumpInst.rewriteFileFormat4=1

device.optimizeWrites=0

device.rawWriteLogEn=1

 

device.delay_time = 0

#-------------------------------------------------------------------------------------------------#

AFE.deviceBringup()

 

AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T

  • Hi David,

    Some questions to help debug:

    • Is this configuration for a custom board?
    • What are you sending to the DAC? Is it supposed to be a CW tone?
    • Could you specify what is the frequency per division on the horizontal axis of your picture?
    • I see there is some changed lane Mux settings on the DAC side, did you also account for any lane inversions?
    • What JESD errors are you getting on the DAC side?

    Best,

    Camilo

  • Hi Camilo,

    Is this configuration for a custom board? -> yes.

    What are you sending to the DAC? -> Linear FM.

    Is it supposed to be a CW tone? -> I will try to.

    Could you specify what is the frequency per division on the horizontal axis of your picture? -> It is 2GHz span.

    I see there is some changed lane mux settings on the DAC side, did you also account for any lane inversions? -> If you like to change other lanes, I need change other IO bank.

    What JESD error are you getting on the DAC side? -> No, I don't know how to get the information.

  • Hi Camilo,

    I made a single tone pulse signal.

    When I transmit the single tone pulse, The spectrum looks like below image.

    Thank you Camilo

  • Hi Byungsoo,

    I was able to set this up in our bench and see a good DAC output. Then I inverted one of the lanes (Meaning swapping p and n of a differential pair) and was able to see an output similar to yours to recreate the issue.

    This leads us to believe that the issue is that one of your SerDes lanes is inverted in polarity. Could you please double check that the polarity has been accounted for and put a 1 in the parameters below for the lanes that are inverted in layout.

    sysParams.serdesTxLanePolarity =[0,0,0,0,0,0,0,0]#ADC STX1 - 8 Polarity 

    sysParams.serdesRxLanePolarity=[0,0,0,0,0,0,0,0]#DAC SRX1 - 8 Polarity

    If fixing the polarity did not fix the DAC output and you are programming the AFE by converting the python file into a log with the SPI transactions, there should be a section towards the end of the file that read checks registers inside the DAC_JESD_AB and DAC_JESD_CD pages to check for the errors.

    It should be below the comment "//START: Reading the JESD RX states to check if link is established" and there should be two sections like in the example below. Could you provide what is read for each of the registers in that section:

    //START: Reading the JESD RX states to check if link is established
    
    
    WAIT 0.001
    SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
    SPIReadCheck 011b,0,7,00
    SPIReadCheck 011a,0,7,00
    SPIReadCheck 0119,0,7,00
    SPIReadCheck 0118,0,7,00
    SPIReadCheck 011f,0,7,00
    SPIReadCheck 011e,0,7,00
    SPIReadCheck 011d,0,7,00
    SPIReadCheck 011c,0,7,00
    
    //Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])
    
    SPIReadCheck 00ee,0,3,0f
    
    //Read	comma_align_lock_flag=0x0; 	Address(0xee[7:0])
    
    SPIReadCheck 00a2,0,7,aa
    
    //Read	jesd_cs_state=0x0; 	Address(0xa2[7:0],0xa3[7:0])
    
    SPIReadCheck 00a6,0,7,00
    
    //Read	jesd_buf_state=0x0; 	Address(0xa6[7:0],0xa7[7:0])
    
    
    //END: Done reading the JESD RX states to check if link is established
    
    
    //START: Reading the JESD RX states to check if link is established
    
    
    WAIT 0.001
    SPIWrite 0016,08,0,7	//dac_jesd=0x2; 	Address(0x16[7:2])
    SPIReadCheck 011b,0,7,00
    SPIReadCheck 011a,0,7,00
    SPIReadCheck 0119,0,7,00
    SPIReadCheck 0118,0,7,00
    SPIReadCheck 011f,0,7,00
    SPIReadCheck 011e,0,7,00
    SPIReadCheck 011d,0,7,00
    SPIReadCheck 011c,0,7,00
    
    //Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])
    
    SPIReadCheck 00ee,0,3,0f
    
    //Read	comma_align_lock_flag=0x0; 	Address(0xee[7:0])
    
    SPIReadCheck 00a2,0,7,aa
    
    //Read	jesd_cs_state=0x0; 	Address(0xa2[7:0],0xa3[7:0])
    
    SPIReadCheck 00a6,0,7,00
    
    //Read	jesd_buf_state=0x0; 	Address(0xa6[7:0],0xa7[7:0])
    
    
    //END: Done reading the JESD RX states to check if link is established
    
    SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

    The registers that are checked in each of the DAC pages are registers 0x118 through 0x11f, 0xa2, 0xa6, and 0xee.

    Best,

    Camilo

  • Hi Camilo,

    I checked my board schematic. I did not connect opposite way. Even I connected the lanes. I set the polarity [False,True,True,False,False,False,False,False].

    In that case, I can not see any pulse.

    I need change some function to answer you like to know.

    Thank you.

  • Hi Byungsoo,

    Just to verify, did you also try once with sysParams.serdesRxLanePolarity=[0,1,0,0,0,0,0,0] and another time with sysParams.serdesRxLanePolarity=[0,0,1,0,0,0,0,0] ?

    If those two things did not work and you are programming the AFE by converting the python file into a log with the SPI transactions, there should be a section towards the end of the file that read checks registers inside the DAC_JESD_AB and DAC_JESD_CD pages to check for the errors.

    It should be below the comment "//START: Reading the JESD RX states to check if link is established" and there should be two sections like in the example below. Could you provide what is read for each of the registers in that section:

    //START: Reading the JESD RX states to check if link is established
    
    
    WAIT 0.001
    SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
    SPIReadCheck 011b,0,7,00
    SPIReadCheck 011a,0,7,00
    SPIReadCheck 0119,0,7,00
    SPIReadCheck 0118,0,7,00
    SPIReadCheck 011f,0,7,00
    SPIReadCheck 011e,0,7,00
    SPIReadCheck 011d,0,7,00
    SPIReadCheck 011c,0,7,00
    
    //Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])
    
    SPIReadCheck 00ee,0,3,0f
    
    //Read	comma_align_lock_flag=0x0; 	Address(0xee[7:0])
    
    SPIReadCheck 00a2,0,7,aa
    
    //Read	jesd_cs_state=0x0; 	Address(0xa2[7:0],0xa3[7:0])
    
    SPIReadCheck 00a6,0,7,00
    
    //Read	jesd_buf_state=0x0; 	Address(0xa6[7:0],0xa7[7:0])
    
    
    //END: Done reading the JESD RX states to check if link is established
    
    
    //START: Reading the JESD RX states to check if link is established
    
    
    WAIT 0.001
    SPIWrite 0016,08,0,7	//dac_jesd=0x2; 	Address(0x16[7:2])
    SPIReadCheck 011b,0,7,00
    SPIReadCheck 011a,0,7,00
    SPIReadCheck 0119,0,7,00
    SPIReadCheck 0118,0,7,00
    SPIReadCheck 011f,0,7,00
    SPIReadCheck 011e,0,7,00
    SPIReadCheck 011d,0,7,00
    SPIReadCheck 011c,0,7,00
    
    //Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])
    
    SPIReadCheck 00ee,0,3,0f
    
    //Read	comma_align_lock_flag=0x0; 	Address(0xee[7:0])
    
    SPIReadCheck 00a2,0,7,aa
    
    //Read	jesd_cs_state=0x0; 	Address(0xa2[7:0],0xa3[7:0])
    
    SPIReadCheck 00a6,0,7,00
    
    //Read	jesd_buf_state=0x0; 	Address(0xa6[7:0],0xa7[7:0])
    
    
    //END: Done reading the JESD RX states to check if link is established
    
    SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

    The registers that are checked in each of the DAC pages are registers 0x118 through 0x11f, 0xa2, 0xa6, and 0xee.

    Best,

    Camilo

  • Hi Camilo,

    When the sysParams.serdesRxLanePolarity=[0,1,0,0,0,0,0,0] is set, I can see the signal output.

    When the other setting is sysParams.serdesRxLanePolarity=[0,0,1,0,0,0,0,0], I can see the signal output.

    I read back the value for each the address.

    In the DAC_JESD AB : 0x16 = 0x04

    Address, Value

    0x0118, 0x00

    0x0119, 0x00

    0x011A, 0x00

    0x011B, 0x00

    0x011C, 0x00

    0x011D, 0x00

    0x011E, 0x00

    0x011F, 0x00

    0x00EE, 0x00

    0x00A2, 0x00

    0x00A6, 0x00

    In the DAC_JESD CD : 0x16 = 0x08

    Address, Value

    0x0118, 0x00

    0x0119, 0x00

    0x011A, 0x00

    0x011B, 0x00

    0x011C, 0x00

    0x011D, 0x00

    0x011E, 0x00

    0x011F, 0x00

    0x00EE, 0x00

    0x00A2, 0x00

    0x00A6, 0x00

    Thank you.

  • Hi Camilo,

    During I read back the value for each address, The RF Output is follow as 

    And I try to read many times the address, I can not see other values.

    Thank you.

  • Hi Byungsoo,

    It is very odd that you get 0x0 for all of the registers.

    During bringup, when you run the AFE configuration (I am assuming you are programming the AFE from your FPGA after the FPGA starts to send data to the AFE SRX lanes), do any of the read checks or polls fail?

    Best,

    Camilo

  • Hi Camilo,

    When I read the Lane0_f_counter_any_lane_ready and lane1_f_counter_any_lane_ready, I can see a value that is 45 and 47. sometimes both value is 45.
    When I read the link0_buffer_depth and link1_buffer_depth, the value are 0x1F.

    But I read the lane0_f_counter_all_lane_ready and lane1_f_counter_all_lane_ready, the values are zero.

    And the lane0_skew and the lane1_skew is read 0x1F.
    When I read the AFE7950 for some special register, Do I need some operations?

  • Hi Byungsoo,

    Depends on what you mean by special register. Are you setting the page before trying to read the register? For example to read the registers in the DAC JESD page a sequence as below would be used:

    SPIWrite 0016,04,0,7	//dac_jesd=0x1; 	Address(0x16[7:2])
    SPIReadCheck 011b,0,7,00
    SPIReadCheck 011a,0,7,00
    SPIReadCheck 0119,0,7,00
    SPIReadCheck 0118,0,7,00
    SPIReadCheck 011f,0,7,00
    SPIReadCheck 011e,0,7,00
    SPIReadCheck 011d,0,7,00
    SPIReadCheck 011c,0,7,00
    
    //Read	alarms=0x0; 	Address(0x118[7:0],0x119[7:0],0x11a[7:0],0x11b[7:0],0x11c[7:0],0x11c[7:0],0x11d[7:0],0x11e[7:0],0x11f[7:0],0x120[7:0])
    
    SPIReadCheck 00ee,0,3,0f
    
    //Read	comma_align_lock_flag=0xf; 	Address(0xee[7:0])
    
    SPIReadCheck 00a2,0,7,aa
    
    //Read	jesd_cs_state=0xaa; 	Address(0xa2[7:0],0xa3[7:0])
    
    SPIReadCheck 00a6,0,7,aa
    
    //Read	jesd_buf_state=0xff; 	Address(0xa6[7:0],0xa7[7:0])
    
    
    //END: Done reading the JESD RX states to check if link is established
    
    SPIWrite 0016,00,0,7	//dac_jesd=0x0; 	Address(0x16[7:2])

    During bringup, when you run the AFE configuration (I am assuming you are programming the AFE from your FPGA after the FPGA starts to send data to the AFE SRX lanes), do any of the read checks or polls fail?

    Best,

    Camilo

  • Hi Camilo,

    Yes,  I set the page before reading the alarm registers (0x118~0x11F) and 0x00E, 0x00A2, 0x00A6.

    But the result is zero for all of them.

    Other register for example 0x0088, 0x0089, 0x008A are return valid values.

    Could you help me what I can do?

    Thank you.

  • Hi Byungsoo,

    Sorry for the delay on this. It is weird that you can read some but not others. Here are two things to try: 

    1. During the AFE's bringup sequence there are read checks and poll fails. Do any of these fail at bringup? If yes, what is the value read versus the value expected if it is a read check failing.
    2. I am assuming you are also able to set the page and read it back correct? For example, after bringup:
      1. Read register 0x16 which should be 0x00
      2. Write 0x04 to register 0x16
      3. Read register 0x16 to verify the value has changed

    Best,

    Camilo

  • Hi Camilo,

    Thank you for your reply.

    I found the problem. It is came from me. I missed the connection to top module for looking the comma align lock(0x00EE) and cs state(0x00A2), bus state (0x00A6).
    After fixed the problem, I can see 0xFF for the comma align lock (0x00EE) and 0xAA for the cs state (0x00A2), 0xFF for the bus state (0x00A6).

    And I fixed the spectrum problem. It is cause the RBD.

    I have a question. When I use the DAC, I need just 2 lanes. Could you make me to know how to connect 2 lane only between AFE7950 and FPGA?

    Thank you.

  • Hi Byungsoo,

    Glad to hear the issue was resolved.

    In regards to your question, when you mean you only need two lanes do you mean you want to keep the JESD parameters the same and disable one DAC channel to only use one DAC channel with only two lanes enabled? Or do you mean changing the LMFS so that both DAC channels are receiving in the same two lanes and keep both DAC channels enabled?

    Best,

    Camilo

  • Hi Camilo,

    I would like to use one DAC channel with only two lanes enabled. In this case, I like to connect 2 lanes only between AFE7950 and FPGA in physically.

    Is it possible?

    Thank you.

  • Hi Byungsoo,

    To disable one of the channels you can use the parameter below in the configuration file. As an example to enable only TXA it would be as below. 

    sysParams.txEnable = [True,False,False,False]

    Best,

    Camilo