Other Parts Discussed in Thread: AFE7950
Hi Team,
we are using AFE7950 Eval board, and using Latte to program the registers.
Microsemi MPF300 is connected to eval board for waveform generation and reception.
when I program both boards the Link is showing LINK_CD_ERROR (saying that the link parameters mismatched) on the JESD-RX(in fpga).
when I captured ILA waveform in fpga I observed that the received bytes are reversed as shown below
I tried forcing reverse byte order at transceiver output data(which is going to JESD-RX in fpga), then the LINK_CD_ERROR is vanished.
in AFE7950 programming guide there is a register SERDES_INPUT_ORDER_FLIP_DISABLE, will this solve my issue? if yes, please suggest me how to include that in Latte code? if not please suggest us the possible solution..
the used Latte code is attached below.
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_14810; Data Rate = 122.88M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_14810; Data Rate = 122.88M
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode = 0 # RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [24,24,24,24] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
[9500,9500], #Band0, Band1 for RXB
[9500,9500], #Band0, Band1 for RXC
[9500,9500]] #Band0, Band1 for RXD
##### FB #####
sysParams.ddcFactorFb = [6,6] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [9500,9500] #Band0 for FB1 and FB2
sysParams.fbEnable = [False,False]
##### TX #####
sysParams.ducFactorTx = [96,96,96,96] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
[9500,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["14810","14810","14810","14810"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [False,False,False,False]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [8,8,8,8]
sysParams.fbJesdTxK = [8,8]
sysParams.jesdTxLaneMux = [7,1,2,3,6,5,4,0] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["14810","14810","14810","14810"]
sysParams.jesdRxLaneMux = [7,4,2,3,6,5,1,0] #[7,6,2,3,4,5,1,0] #0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [3, 3]
sysParams.jesdRxScr = [False,False,False,False]
sysParams.jesdRxK = [8, 8, 8, 8]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 1474.56 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 245.76 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
#line 119 changes ps
sysParams.useSpiSysref=True
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
Thank you,
Obul
