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AFE7950EVM: Clarification on sampling properties

Daniel Pereira
Prodigy 90 points

Part Number: AFE7950EVM
Other Parts Discussed in Thread: TSW14J57EVM, , AFE7950

Greetings

I need a clarification on the achievable sampling rates of the AFE7950EVM (used in conjunction with a TSW14J57EVM). In the AFE7950 data sheet it explains that the per-channel sampling rate is dependant on the number of DAC and ADC channels being used, but the way the information is explained is somewhat confusing.

Why do 12GSPS DACs only achieve a 1200 (or 2400) MHz bandwidth? From those values it seems that the DACs share a common clock (and the ADCs share their clock with the feeback channels), is that the case? Or are these lower bandwidth values due to the DACs always operating with some level of interpolation?

Thank you in advance for your help.

 Daniel

  • 0
    TI__Expert 5185 points

    Hi Daniel,

    I would suggest looking at section 8.3.8.3 of the AFE7950 datasheet. In this section you can see the different JESD modes supported by the AFE along with the difference input and output rates for the DACs and ADCs respectively. To get the max RF IBW for each of the different modes you must take the input/output data rate and multiply it by 0.8 to account for the DDC/DUC passband so that it does not attenuate your signal.

    For example, if you have the ADC with Fs = 3GSPS and you need to capture a signal with a max IBW of 400MHz, you would need a mode with an interface rate of at least 400*100/80 = 500MHz to account for the decimation filter passband of about 80%.

    Also please keep in mind that the TSW14J57EVM supports a max lane rate of 15Gbps and only supports the 8b10b encoding when looking at the modes.

    In regards to the clocking structure, please refer to figures 5-8 of the “AFE79xx_ConfigurationGuide_SBAA417_Jun2020.pdf” in the secure folder. Which shows the clocking path for different cases.

    The AFE also does not support DDC or DUC bypass for the ADCs and DACs respectively.

    Best,

    Camilo