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AFE7950EVM: How to generate a sine wave signal and send it to AFE7950evm?

xiao mao
Prodigy 40 points
Part Number: AFE7950EVM

Hi Team,

        We purchased AFE7950EVM and tested it together with ZCU102.  I have applied for TI's JESD204B IP.

        I use this source code package: ZCU102-AFE79xx_8b10b10Gbps.  According to document TI204c-Setup.docx, I can see a (NCO+7.68) Mhz signal on the spectrograph.

        I have checked the source code sine_64point.att.sv, and I think the samples_vector array in it is a sine wave signal. Right？

        My question is:

        If I want to generate signals of other frequencies, how to generate this type of array? Can you provide the corresponding tools? Is it through Matlab or Python?

  • 0
    Prodigy 40 points

    By the way, I am in China, is it possible to directly contact the technical support here. Because I think the replies on the forum are relatively slow.

  • 0
    Prodigy 40 points

    Hi Team,

                Our task is urgent, could you please reply to my question?

  • 0 in reply to xiao mao
    TI__Expert 5035 points

    Hi Xiao,

    Sorry for the delay.

    These reference designs include a 64-point sine wave inside the “samples_vector” that is only there to be used for demonstration purposes. 

    You are free to replace the 64-point sine wave with any waveform of your choice as long as you make the changes on the FW for it.

    What we typically see is people use MATLAB or Python to generate their own custom waveforms as you have described. MATLAB has packages for this.

    Best,

    Camilo

  • 0 in reply to Camilo Garcia Trujillo
    Prodigy 40 points

    Hi Camilo，

               Thank you for your reply.

                I would like to replace the ‘samples_vector’ with a waveform of 1024 points, as we use a linear frequency modulation signal with a bandwidth of 100MHz， The sampling rate is 491.52MHz.  So I changed the TX_LANE_DATA_WIDTH in "jesd_link_params.vh" to 1024.

                 Is it feasible for me to do this？

                  The LMFSHdTx  for JESD 204B is: 4-4-2-1-0， What is the transmission data format for JESD204B when using TI's JESD204B  IP core?

              

  • 0 in reply to xiao mao
    TI__Genius 17781 points

    Hi Xiao,

    The lane data width should not be updated to 1024. For the ZCU102 we are limited to a value of 32 or 64 for the lane data width. 

    In order to change the 64-point sine wave to your custom waveform, you should first create your waveform and then in the vivado project the refdesign_tx.sv document should be updated to cycle through 1024 point signal, instead of our example sine wave,and pack 4 16 bits samples over the 8 Tx lanes (each lane is 64 bits wide). 

    Regards,

    David Chaparro

  • 0 in reply to David Chaparro
    Prodigy 40 points

    Hi David,

              Thank you for your answer. I have another question：

               The DataRate in the program is 491.52MSPS, with 64 sampling points, so the sine wave frequency is 491.52M/64=7.68Mhz,  And so on:，If the sine wave frequency is 7.68Mhz*2=15.36Mhz，The  number of sampling points is 32, Right ？ I need to repeat these 32 points twice and put them in the ‘samples_vector’ array.  That is to say, the signal frequency of FPGA needs to be a multiple of 7.68 MHz, and the sampling point needs to be divisible by 64, right? 

               What should I do if the signal frequency is 10MHz waveform and the number of sampling points is 64, which is not a complete waveform?

               So if I generate a linear frequency modulation signal using Matlab script and the frequency is not fixed, how should I modify the number of sampling points?

    How should I modify the code?

              

  • 0 in reply to xiao mao
    TI__Expert 5035 points

    Hi Xiao,

    This is correct “The DataRate in the program is 491.52MSPS, with 64 sampling points, so the sine wave frequency is 491.52M/64=7.68Mhz,”. The goal of these reference design is to show how you can get the JESD link up between the part and one of the common FPGA evaluation kits in the market.

    You can add any stage after that to handle adding your own waveforms to the design. A way to do this would be to increase the number of points such that your desired signal can fit into the design.

    In regards to your question of how to get an exact 10MHz with only 64 points. The answer is that you can’t unless you have the FPGA generate the waveform as it plays it out.

    Best,

    Camilo