Tool/software:
Hello,
I have a question regarding the SYSREF timing relation with DACCLK, when using the DAC's internal PLL to generate the sampling clock.
In our system we apply a 200 MHz clock to DACCLK input.
We use the internal DAC PLL to generate 6600 MHz as the DAC's sampling clock; our JESD204 settings are LMFSD=42111 with a rate of 2750MBps.
We then get a DACCLKOUT signal, (6600/3=2200) which is divided externally by 4, to derive an FPGA JESD204 clock of 550MHz.
The FPGA JESD204 core is timed at 68.75MHz.
So, far so good.
We need also to generate a SYSREF signal from within the FPGA. The JESD204 core example creates this clock from the JESD core clock of 68.75MHz, as per this equation SYSREF = DR/(20*N) (K=20).
The datasheet says that SYSREF must have a fixed relation with DACCLK.
However, I fail to see how the generated SYSREF edges (from 68.75MHz) will have a constant relation with the input DAC clock of 200 MHz.
If I generate SYSREF from the 200MHz clock, then I would not be able to satisfy the SYSREF = DR/(K*N) equation.
Did I misunderstand anything? What is the correct approach to satisfy the requirements?
Thanks,
Ilias
