Tool/software:
Hello E2E Experts,
Good day,
Data is not correct when I transmit or receive data from TSW40RF80EVM by JESD204B. I am trying to read from ADC and write from DAC with Xilinx FPGA ZC706. I input some sine waves but the output seems messy. The same things happened to ADC as well. The data from ADC is also messy. It didn't change when I tried to input the sine or ramp signal.
I have the same K and F values on both sides of FPGA and DAC. I used configure file with the GUI, then changed the L, K, and F as the register value on FPGA Xilinx JESD204b IP. But when I read the alarms on DAC, it shows multiframe alignment errors. The clock I use is from the TSW40RF80EVM. There shouldn't be a clock or setting issues.
I attached the picture of my setting, clock, and results. Are there any mistakes in my setup? How to read and write correctly? Is there anything I should take care of?
Screenshot 2024-09-04 231015.zip
Regards,
TI-CSC