AFE7921: AFE7921 link not stably

zhansheng chen

Part Number: AFE7921

Tool/software:

Hi,

We are use AFE7921 with some question.

In the past, we used bandwidth with 200M,our AFE7921 config is below , and our sysref is 3.84MHz，JESD TX and JESD RX rate is 9.8304Gbps， it works stably.

sysParams.FRef = 245.76

sysParams.FadcRx = 2949.1

sysParams.Fdac = 2949.12*3

sysParams.ddcFactorRx = [12,12,12,12]

sysParams.ducFactorTx = [36,36,36,36]

Now we used bandwidth with 100M to save FPGA resources and power, and sysref is 3.84MHz,,our AFE7921 config is below,the clk and ADC/DAC rate was the same,the DDC value is doubled .JESD TX and JESD RX rate is 4.9152Gbps But it works is not stably.,some times link down,and some times link up and then link down toggle.

sysParams.FRef = 245.76

sysParams.FadcRx = 2949.1

sysParams.Fdac = 2949.12*3

sysParams.ddcFactorRx = [24,24,24,24]

sysParams.ducFactorTx = [72,72,72,72]

We also try to change ADC/DAC rate,,our AFE7921 config is below. but the phenomenon is the same,it also works is not stably.,some times link down,and some times link up and then link down toggle.

sysParams.FRef = 245.76

sysParams.FadcRx = 1474.56

sysParams.Fdac = 1474.56*3

sysParams.ddcFactorRx = [12,12,12,12]

sysParams.ducFactorTx = [36,36,36,36]

4 months ago

0 Aman Thombre 4 months ago

TI__Expert 4490 points

Hi Mr. Chen,

Is this in any way related to this other E2E asking for a new Latte version? https://e2e.ti.com/support/rf-microwave-group/rf-microwave/f/rf-microwave-forum/1415771/afe7921-some-question-about-latte-and-afe79xxevm_-gui-version

If so, please try with the latest version of AFE79xx Latte. Also, please try setting FadcRx = 2949.12, not 2949.1.

If these fixes do not work, please send me your configuration script (we can do this over private E2E message if you'd like) and I can take a look on my setup.

Thanks,

Aman

0 zhansheng chen 3 months ago in reply to Aman Thombre

Prodigy 140 points

Hi,

My copy is missing 2,the FadcRx is 2949.12, When I missing 2 when I copy

Our config is below

'''
Validation :  AFE79xx Library Version 
				v1.67, v1.74
Case			RX					TX						   FB						CLK					Notes
----	-----------------	  -----------------			-----------------			-----------			------------
1		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in interleaved mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
		
2		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in straight mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
'''
setupParams.skipFpga 				= 1
sysParams							=	AFE.systemParams
setupParams.fpgaRefClk 				= 122.88	
AFE.systemStatus.loadTrims			= 1

sysParams.FRef                    	= 122.88
sysParams.FadcRx                  	= 1474.56
sysParams.FadcFb				  	= 1474.56
sysParams.Fdac                    	= 1474.56*3

sysParams.enableDacInterleavedMode	= True 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx                	=['24410', '24410', '24410', '24410']	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["24410","24410"]
sysParams.LMFSHdTx                	= ["24410","24410","24410","24410"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,4,5,2,3,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux				= [0,1,4,5,2,3,6,7]	
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd					= [4, 4]

sysParams.rxJesdTxScr				= [True,True,True,True]
sysParams.fbJesdTxScr				= [False,False]
sysParams.jesdRxScr					= [True,True,True,True]

sysParams.rxJesdTxK					= [32,32,32,32]
sysParams.fbJesdTxK					= [32,32]
sysParams.jesdRxK					= [16,16,16,16]

sysParams.ncoFreqMode 				= "1KHz"
	
sysParams.txNco0					= 	[[1950,2600],		#Band0, Band1 for TxA for NCO0
										[1747.5,2600],        #Band0, Band1 for TxB for NCO0
										[2535,2600],        #Band0, Band1 for TxC for NCO0
										[3400,2600]]        #Band0, Band1 for TxD for NCO0

sysParams.rxNco0					= 	[[2140,2600],		#Band0, Band1 for RxA for NCO0
										[1842.5,2600],        #Band0, Band1 for RxB for NCO0
										[2655,2600],        #Band0, Band1 for RxC for NCO0
										[3400,2600]]        #Band0, Band1 for RxD for NCO0

sysParams.fbNco0					= 	[2200,2200]			#FBA, FBC for NCO0
sysParams.fbNco1					= 	[2200,2200]			#FBA, FBC for NCO1
sysParams.fbNco2					= 	[2200,2200]			#FBA, FBC for NCO2
sysParams.fbNco3					= 	[2200,2200]			#FBA, FBC for NCO3

sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

sysParams.ddcFactorRx             	= [12,12,12,12]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [6,6]
sysParams.ducFactorTx             	= [36,36,36,36]

AFE.systemStatus.loadTrims			=1

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	2949.12/1024
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\AFE7921_config_24410_1_12288.txt")
logDumpInst.logFormat				= 0x0f
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 1
sysParams.jesdCDLvdsSync			= 1
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= True

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'ADC_SYNC1',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'DAC_SYNC0',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True
		

## Initiates LMK04828 and AFE79xx Bring-up
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)

0 Aman Thombre 3 months ago in reply to zhansheng chen

TI__Expert 4490 points

Hi Mr. Chen,

I have made the following changes to your configuration script:

Change FadcRx and FadcFb = 2949.12, Fdac = 2949.12*3. I set this as with Fdac = 1474.56*3, some TX NCO will be in the second Nyquist zone, where DAC interleaved mode is not supported.

Change DDC and DUC factors - needed as I changed FadcRx, FadcFb, and Fdac. I changed these to the factors you were using with Fadc = 2949.12.

sysParams.ddcFactorRx             	= [24,24,24,24]
sysParams.ddcFactorFb             	= [24,24]
sysParams.ducFactorTx             	= [72,72,72,72]

Set skipFpga = 0. This is needed for the TSW14J58 EVM FPGA. If you are using TSW14J57 EVM FPGA and using HSDC Pro to set it up, please set this back to setupParams.skipFpga = 1 at the top of the configuration script. This will not change the configuration file generated by Latte, this is just for setup of the FPGA EVM.
Change fpgaRefClk and Fref to 245.76. 122.88 MHz is not supported as reference clock for TSW14J58 FPGA. I changed Fref to 245.76 as this is what you had specified above, I'm not sure if this as 122.88 is intended?
```
setupParams.fpgaRefClk 				= 245.76
sysParams.FRef                    	= 245.76
```
Set sysParams.syncLoopBack = False. This parameter is enabled to use the hardware sync pins, but the AFE7921 EVM + TSW14J48 EVM setup does not support this well. It is possible to get a link up when setting syncLoopBack=True, but these require some extra commands and you will be unable to test RX as captures are not supported when syncLoopBack is enabled. When you generate the .txt configuration file, you can set syncLoopBack=True to set this parameter for the configuration file.

With the above changes, I am able to get a successful bring-up of your configuration every time.

Please see below for the updated configuration file:

'''
Validation :  AFE79xx Library Version 
				v1.67, v1.74
Case			RX					TX						   FB						CLK					Notes
----	-----------------	  -----------------			-----------------			-----------			------------
1		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in interleaved mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
		
2		245.76Msps, 24410     491.52Msps, 44210			491.52Msps, 22210			FADC=2949.12M       DAC in straight mode
		SerDes=9830.4Mbps     SerDes=9830.4Mbps			SerDes=9830.4Mbps			FDAC=8847.36M
		PLL0, NCO=3500M		  PLL0, NCO=3500M			NCO=3500M                   REF=491.52M
'''
setupParams.skipFpga 				= 0
sysParams							=	AFE.systemParams
setupParams.fpgaRefClk 				= 245.76	
AFE.systemStatus.loadTrims			= 1

sysParams.FRef                    	= 245.76
sysParams.FadcRx                  	= 2949.12
sysParams.FadcFb				  	= 2949.12
sysParams.Fdac                    	= 2949.12*3

sysParams.enableDacInterleavedMode	= True 					#DAC interleave mode to save power consumption. Fs/2 - Fin spur occurs

sysParams.modeTdd 					= 0		
										# 0- Single TDD Pin for all Channels
										# 1- Separate Control for 2T/2R/1F
										# 2- Separate Control for 1T/1R/1F			

sysParams.topLevelSystemMode		= 'StaticTDDMode'
sysParams.RRFMode 					= 0   #4T4R2F FDD mode
sysParams.jesdSystemMode			= [3,3]
										#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb-fb
										#SystemMode 1:	1R1F-FDD						; rx1-rx1-fb-fb
										#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
										#SystemMode 3:	1R								; rx1-rx1-rx1-rx1
										#SystemMode 4:	1F								; fb-fb-fb-fb
										#SystemMode 5:	1R1F-TDD						; rx1/fb-rx1/fb-rx1/fb-rx1/fb
										#SystemMode 8:	1R1F-TDD 1R-FDD	(FB-2Lanes)(RX1 RX2 interchanged)		; rx2/fb-rx2/fb-rx1-rx1


sysParams.jesdLoopbackEn			= 0 #Make it 1 to Enable the JESDTX to JESDRX internal loopback
sysParams.LMFSHdRx                	=['24410', '24410', '24410', '24410']	
										# The 2nd and 4th are valid only for jesdSystemMode values in (2,6,7,8). For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb                	= ["24410","24410"]
sysParams.LMFSHdTx                	= ["24410","24410","24410","24410"]
sysParams.jesdTxProtocol            = [0,0]
sysParams.jesdRxProtocol            = [0,0]
sysParams.serdesFirmware			= True 		# If you want to lead any firmware, please speify the path here. Otherwise it will not write any firmware
sysParams.jesdTxLaneMux				= [0,1,4,5,2,3,6,7]	
												# Enter which lanes you want in each location. 
												# Note that across 2T Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2T, this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxLaneMux				= [0,1,4,5,2,3,6,7]	
												# Enter which lanes you want in each location.
												# Note that across 2R Mux is not possible in 0.5.
												# For example, if you want to exchange the first two lines of each 2R, this should be [[1,0,2,3],[5,4,6,7]]

sysParams.jesdRxRbd					= [4, 4]

sysParams.rxJesdTxScr				= [True,True,True,True]
sysParams.fbJesdTxScr				= [False,False]
sysParams.jesdRxScr					= [True,True,True,True]

sysParams.rxJesdTxK					= [32,32,32,32]
sysParams.fbJesdTxK					= [32,32]
sysParams.jesdRxK					= [16,16,16,16]

sysParams.ncoFreqMode 				= "1KHz"
	
sysParams.txNco0					= 	[[1950,2600],		#Band0, Band1 for TxA for NCO0
										[1747.5,2600],        #Band0, Band1 for TxB for NCO0
										[2535,2600],        #Band0, Band1 for TxC for NCO0
										[3400,2600]]        #Band0, Band1 for TxD for NCO0

sysParams.rxNco0					= 	[[2140,2600],		#Band0, Band1 for RxA for NCO0
										[1842.5,2600],        #Band0, Band1 for RxB for NCO0
										[2655,2600],        #Band0, Band1 for RxC for NCO0
										[3400,2600]]        #Band0, Band1 for RxD for NCO0

sysParams.fbNco0					= 	[2200,2200]			#FBA, FBC for NCO0
sysParams.fbNco1					= 	[2200,2200]			#FBA, FBC for NCO1
sysParams.fbNco2					= 	[2200,2200]			#FBA, FBC for NCO2
sysParams.fbNco3					= 	[2200,2200]			#FBA, FBC for NCO3

sysParams.numBandsRx				= [0]*4					# 0 for single, 1 for dual
sysParams.numBandsFb				= [0,0]				
sysParams.numBandsTx				= [0,0,0,0]

sysParams.ddcFactorRx             	= [24,24,24,24]			# DDC decimation factor for RX A, B, C and D
sysParams.ddcFactorFb             	= [24,24]
sysParams.ducFactorTx             	= [72,72,72,72]

AFE.systemStatus.loadTrims			=1

## The following parameters sets up the LMK04828 clocking schemes
lmkParams.pllEn						=	True#False
lmkParams.inputClk					=	1474.56#737.28
lmkParams.sysrefFreq				=	2949.12/1024
lmkParams.lmkFrefClk				=	True

## The following parameters sets up the register and macro dumps
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\AFE7921_config_24410_1_12288.txt")
logDumpInst.logFormat				= 0x0f
logDumpInst.rewriteFile				= 1
logDumpInst.rewriteFileFormat4		= 1
device.optimizeWrites				= 0
device.rawWriteLogEn				= 1

## The following parameters sets up the SYNCIN and SYNCOUT to interface with the TSW14J57
sysParams.jesdABLvdsSync			= 1
sysParams.jesdCDLvdsSync			= 1
sysParams.rxJesdTxSyncMux			= [0,0,0,0]
sysParams.fbJesdTxSyncMux			= [0,0]
sysParams.jesdRxSyncMux				= [0,0,0,0]		#[0,0,1,1]
sysParams.syncLoopBack				= False

# ## The following parameters sets up the AGC
# sysParams.agcParams[0].agcMode = 1 ##internal AGC
# sysParams.agcParams[0].gpioRstEnable = 0 ##disable GPIO based reset to AGC detector 
# sysParams.agcParams[0].atken = [0, 1, 0] ##enable big and small step attack
# sysParams.agcParams[0].decayen = [0,1,0] ##enable big and small step decay
# sysParams.agcParams[0].atksize = [2,1,0] ## bigs step = 2dB, small step = 1dB
# sysParams.agcParams[0].decaysize = [2,1,0] ##big step = 2dB, small step = 1dB
# sysParams.agcParams[0].atkthreshold = [-1, -2, -14] ##attack threshold
# sysParams.agcParams[0].decaythreshold = [-14, -6, -20] ##decay threshold
# sysParams.agcParams[0].atkwinlength = [170, 170] ## detector time constant expressed inn absolute time in ns. 
# sysParams.agcParams[0].decaywinlength = 87380 ##detector time constant expressed in absolute time in ns. All detectors use the same value for decay time constant
# sysParams.agcParams[0].atkNumHitsAbs = [8,8] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].decayNumHitsAbs = [100,100] ##absolute number of times signal crosses threshold. These crossing are with respect to the FADC/8 clock
# sysParams.agcParams[0].minDsaAttn = 0 ##minimum DSA attenuation used by AGC
# sysParams.agcParams[0].maxDsaAttn = 22 ##maximum DSA attenuation used by AGC
# sysParams.agcParams[0].totalGainRange = 22 ##total gain range used by ALC for gain compensation
# sysParams.agcParams[0].minAttnAlc = 0 ##minimum attenuation used by ALC for compensation when useMinAttnAgc = 0
# sysParams.agcParams[0].useMinAttnAgc = 1 ##enable ALC to use minimum attenuation from AGC for which compensation is required.
# sysParams.agcParams[0].alcEn = 1
# sysParams.agcParams[0].alcMode = 0 ##floating point DGC
# sysParams.agcParams[0].fltPtMode = 0 ##if exponent > 0, dont send MSB
# sysParams.agcParams[0].fltPtFmt = 1 ##3 bit exponent


## The following parameters sets up the GPIOs
sysParams.gpioMapping={
		'H8': 'ADC_SYNC0',
		'H7': 'ADC_SYNC1',
		'N8': 'ADC_SYNC2',
		'N7': 'ADC_SYNC3',
		'H9': 'DAC_SYNC0',
		'G9': 'DAC_SYNC1',
		'N9': 'DAC_SYNC2',
		'P9': 'DAC_SYNC3',
		'P14': 'GLOBAL_PDN',
		'K14': 'FBABTDD',
		'R6': 'FBCDTDD',
		'H15': ['TXATDD','TXBTDD'],
		'V5': ['TXCTDD','TXDTDD'],
		'E7': ['RXATDD','RXBTDD'],
		'R15': ['RXCTDD','RXDTDD']}
		
#AFE.systemParams.papParams[0]['enable'] = True
#AFE.systemParams.papParams[1]['enable'] = True
#AFE.systemParams.papParams[2]['enable'] = True
#AFE.systemParams.papParams[3]['enable'] = True


## Initiates LMK04828 and AFE79xx Bring-up
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)

Hope this is helpful for you! Please let me know if you have any follow-up questions.

Thanks,

Aman

0 zhansheng chen 3 months ago in reply to Aman Thombre

Prodigy 140 points

Hi，

1.We also change FadcRx and FadcFb = 2949.12 and Fdac = 2949.12*3 ,it also the same phenomenon.

2.When we change FadcRx and FadcFb = 2949.12 and Fdac = 2949.12*3,Our DDC was change to adapt our lane rate,our DDC is change to below

sysParams.ddcFactorRx = [24,24,24,24] # DDC decimation factor for RX A, B, C and D

sysParams.ddcFactorFb = [6,6]

sysParams.ducFactorTx = [72,72,72,72]

but it also the same phenomenon,link not stably

3.We don't have any EVM,We use our board to debug

4.We also try to change refclk to 245.76MHz.And also change sysParams.FRef = 245.76,but the same phenomenon,link not stably.

5.We are use FPGA to detect SYNC,When is not link up. we test the sync pin waveform is below

And also when is link up normally，the sync pin waveform is not very good,it's below

0 Kang Hsia 3 months ago in reply to zhansheng chen

TI__Guru 72579 points

Hi Mr. Chen,

Two suggestion:

1. Most likely you will have to adjust the AFE7921 TX JESD204 Receiver buffer. To do so, please utilize the C API setGoodRbd(). You may find details in the document below:

https://www.ti.com/lit/an/sbaa543/sbaa543.pdf

2. Would you be able to help us analyze the current issue by checking the following alarms? This will help us understand the next steps. Thank you.

3. For optimal phase noise performance of the AFE7921, we recommend keeping the Fref at 491.52MHz as this will ensure the PFD rate is at the highest and fastest level.

-Kang

0 zhansheng chen 3 months ago in reply to Kang Hsia

Prodigy 140 points

OK,We try to use API to read this status

0 Kang Hsia 3 months ago in reply to zhansheng chen

TI__Guru 72579 points

Hi Mr. Chen,

Please read the API and keep us updated. Thank you.

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AFE7921: AFE7921 link not stably