AFE7950: SYNC

Hi,

Are you able to probe on the AFE side and verify that the AFE sees the SYNC from the FPGA? The error that you are seeing is most commonly seen when the AFE is not receiving the SYNC signal.

In your configuration are you using CMOS Syncor LVDS Sync? 

Regards,

David Chaparro 

The settings generated by Latte are used.

"S1_OnboardClk_RX_250M_TX_FB_500M.py" recognizes SYNC and outputs data.

"S3_OnboardClk_RX_TX_500M_FB_disabled.py" does not recognize SYNC and remains /k28.5/.

Hi,

Were there any updates to the two files? Can you check that the sysParams.syncLoopBack parameter is set to 'True'?

Regards,

David Chaparro 

Both are "sysParams.syncloopback = true".
The change location has been changed to "Sysparams.rxnco0" to "950" and "logdumpinst.logformat = 0x40".
This change is made both.
There are no other changes.

Hi Yuuki,

On the FPGA side are you using the Xilinx JESD IP or the TI JESD204c IP?

On the FPGA side do you see it pulling the SYNC signal 'HIGH' and if you probe on the AFE7950EVM do you see the SYNC signal close to the AFE do you see the signal go 'HIGH'? 

Ideally the SYNC signal should be held high then the FPGA should pull it low and the AFE should send the  /k28.5/ and when the FPGA locks to this it should pull the SYNC signal back high and the AFE should start sending data.

Regards,

David Chaparro