AFE7950EVM: SPI Bringup Guide

Jose Perez

Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950

Tool/software:

Good morning,

I'm trying to configure the AFE79xx SPI bringup Guide With Xilinx FPGAs example provided with documentation of the AFE7950EVM. In order to be able to create the constrains, I'm using as reference the table provided at the User Guide PDF which gives an overview of the pin's connections. I was looking for the pins related with SPI communication with LMK block through the FMC connector. However, the schematic of the board shows that the only way to get access to those paths is through USB connection.

Am I missing something? Or the connection reference at AFE79xx SPI bringup Guide With Xilinx FPGAs example related with LMK through the FMC connector is not required?

By the way, I am working with a Versal board, VCK190.

Any help would be appreciated.

Thanks for your time.

Best regards.

3 months ago

0 Elan 3 months ago

Prodigy 120 points

Hi Jose,

For programming the LMK you need to connect jumper wire from the resistor. you have to connect R9 to R242, R88 to R248 and R87 to R249 using jumper wire.

Is the document name is SBAU412A??

Regards,

Bala

0 Jose Perez 2 months ago in reply to Elan

Prodigy 20 points

Hi Bala,

Yes it is, but without final A.

In which document can I find a reference of the changes you suggested?

Regards,

Jose

+1 Elan 2 months ago in reply to Jose Perez

Prodigy 120 points

Hi Jose,

https://www.ti.com/lit/ug/sbau412a/sbau412a.pdf

Reagrds,

Bala

0 Jose Perez 2 months ago in reply to Elan

Prodigy 20 points

Hi Bala,

Thanks for the link. The document related placed at AFE79xx family high-speed transceiver design & support files, Secure Resources area, is not up to date, just for record.

Thanks a lot.

Jose.

0 Elan 2 months ago in reply to Jose Perez

Prodigy 120 points

Hi Jose,

I am not able to get what you are saying. And also I have one doubt in the c code there are some functions like rst_afe79(), enable_JESDIP(), enable_JESDTXIP().

Do you know anything about these functions?

Reagrds,

Bala

0 Jose Perez 2 months ago in reply to Elan

Prodigy 20 points

Hi Bala,

I took a look to the functions. Looks like functions that build a register's value of the AFE7950. Which would be the question?

Regards,

Jose

0 Elan 2 months ago in reply to Jose Perez

Prodigy 120 points

Hi Jose,

In those functions we will toggle some bits named RSTn, JESD TXRST, JESD RSTn. I think we need to send these signals to AFE79xx, so the resets will happen. If you have any idea regarding these means you can share and I am new to these AFE thing. I need assistance for these.

Regards,

Bala

0 Jose Perez 2 months ago in reply to Elan

Prodigy 20 points

Hi Bala,

If you have not done it yet, I recommend you requesting access to the documentation of the board, the access to the request form is below the description into a Importat Note banner. https://www.ti.com/tool/AFE7950EVM?keyMatch=AFE7950EVM&tisearch=universal_search&usecase=hardware

Between that documentation, there is an example of SPI communication design with software to be loaded to the FPGA with Vitis. The main function of that software, makes calls functions required to configure the AFE7950EVM board through FMC connector with SPI protocol.

I am not sure if this answer is oriented to what concerns you.

Regards,

Jose.

0 Elan 2 months ago in reply to Jose Perez

Prodigy 120 points

Hi Jose,

Thanks for your assistance.

I don't know about the thing what you have said now. I am a beginner so I don't know much about these vivado and AFE79xx. So I will send my screenshot of design, If you find anything missing in the design means you can say me. I need assistance for this.

Regards,

Bala

0 Jose Perez 2 months ago in reply to Elan

Prodigy 20 points

Hi Bala,

Your design looks good to me. Only tricky point I detect is remember to properly assign in constrains file the pins for SPI enable bits.

Regards,

Jose

+1 David Chaparro 2 months ago in reply to Jose Perez

TI__Genius 14961 points

Jose,

The app note that Bala linked should be followed in order for the FPGA to bringup the AFE over the FMC. One important thing to note about the SPI design with the Versal dev kits is that there are different I/O voltage levels between the AFE EVM and the FPGA. The AFE SPI is at 1.8V and the FPGA is at 1.2V so a level translator would be recommended between the two. For testing on the AFE EVM, which does not have a level translator on the SPI, what could be done in place of that is a voltage divider on the signals being sent to the FPGA, which will require making hardware mods.

Regards,

David Chaparro

0 Jose Perez 2 months ago in reply to David Chaparro

Prodigy 20 points

David,

Is there any reference design or reference documentation that defines the example for a Versal?

Regards,

Jose.

0 David Chaparro 2 months ago in reply to Jose Perez

TI__Genius 14961 points

Hi Joes,

The TI JESD204C IP can be requested through the link below.

https://www.ti.com/drr/opn/TI204C-IP

Regards,

David Chaparro

RF & microwave

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AFE7950EVM: SPI Bringup Guide