Tool/software:
Hello,
We are designing a custom AFE7950EVM and working with JESD204C. We need confirmation regarding the high-speed interface PCB layout.
The ADCs have a sampling frequency of 3 GSPS, which implies a Nyquist frequency of 1.5 GHz. However, since the input RF signal bandwidth is 12 GHz, we understand that the analog portion of the design, including PCB traces, must support frequencies up to the input signal to avoid any distortion or loss before down-conversion. To address this, we have routed the traces to support frequencies up to 24 GHz (accounting for the 2nd harmonic) for both RX and TX paths.
For the JESD204C SERDES interface, with a maximum lane rate of 29.5 Gbps, the fundamental frequency content is approximately half the bit rate (14.75 GHz). Given the rise and fall times of these high-speed signals, we've accounted for harmonics and routed the JESD lines to support up to 44.25 GHz (the 3rd harmonic).
Could you kindly confirm whether our approach is correct and sufficient for the design to function as intended? Would you recommend any adjustments before we proceed?
Thank you for your assistance. We look forward to your feedback.
Best regards,
