AFE7900EVM: Enabling JESDIP through FMC for SPI Bringup

Tool/software:

Hi,

I am working with the ZCU102 board and AFE7900 EVM, trying to program the AFE and LMK chips through SPI. When programming through Latte, we typically use VIOs in Vivado to send reset signals such as master_reset_n, ext_rx_sync_reset, and ext_tx_sync_reset. However, I am transitioning to C code for this process and noticed functions like rst_afe79(), enable_JESDIP(), and enable_JESDTXIP(). In these functions, I toggle several signals, including:

• TXTDD 0th bit
• RXTDD 1st bit
• RSTn  2nd bit
• JESD TXRST 3rd bit
• JESD RSTn  4th bit

I understand that these signals need to be sent through the FMC connector to the AFE7900 to control the resets. However, I am unsure of which specific FMC pins I need to map these signals to in Vivado.

Could anyone provide guidance on how to determine the correct FMC pins for these signals, or if there is a reference mapping for ZCU102 and AFE7900 that I could follow?

Any help or resources would be greatly appreciated!

Regards,
Bala