AFE7900: Design guide & JESD interface format needed

youngjae Kim

Prodigy 10 points

Part Number: AFE7900

Tool/software:

Hello

Recently I'm designing a small system with AFE7900 + Xilinx MPSoC.

I'm trying to use L band(950~1450) RF signal(500MHz BW) and want to downconvert to DC (vice versa).

I think I should run ADC with 3000MHz rate(real), and mixor down to DC and down sample to 500MHz( I/Q )

1) JESD interface : I can't find I/Q bit(Byte) mapping format of JESD204B. (in accordance with input resolution)

2) What is total interface data bit width of JESD204B and interface speed? ( Can I find this in LMFSHd combination? ; F - octet / frame mean it ? )

Can I select wider bit width with lower interface speed while interfacing data rate is identical?

Thanks in advance.

BR.

Youngjae

3 months ago

0 Camilo Garcia Trujillo 3 months ago

TI__Expert 4925 points

Hi Youngjae,

In regards to the JESD you can refer to section of 8.3.8.3 of the AFE7900 datasheet. Where you can find some of the different JESD modes listed by input/output rate.

You can also use the Excel sheet below as a guide on how to calculate lane rate for different parameters:

Lane Rate Calc_cust.xlsx

We can also create a script for your desired mode if you can provide the information in the table below. It is worth noting that you will want a sample rate such that the Fs/2 will be away from your cand of operation (950 - 1450).

TX
# of TX enabled	?
Fs DAC [GSPS]	?
Single or Dual Band	?
Interpolation	?
FB
# of FB enabled	?
Fs ADC[GSPS]	?
Single or Dual Band	?
Decimation	?
RX
# of RX enabled	?
Fs ADC[GSPS]	?
Single or Dual Band	?
Decimation	?
JESD
Encoding (If not sure we can pick for you)	?
Available Lanes on FPGA	?
Max Lane Rate Supported by FPGA [Gbps]	?
Deterministic Latency and/or Multi-Chip Synchronization Required (Y/N) (Note for multi-chip synchronization DC couple SYSREF is recommended)	?
Clocking
Use AFE internal PLL	?

Best,

Camilo

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AFE7900: Design guide & JESD interface format needed