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AFE7951: Synchronize multiple components

Maor Bouhadana
Prodigy 50 points
Part Number: AFE7951

Tool/software:

Hi, I'm trying to find a guide or explanation for using several AFE7951 chips that will be synchronized in frequency and time.

I have several FPGAs, each connected in JESD204 to the AFE. How do I ensure that the 4 Rx of one chip is synchronized with the other chip?

Do I need a common LO, or is the REF CLK enough? Does the SYSREF of the chips need to be common or not? there are few registers to set?

what is the entire sync mechanism?

THANK YOU!

  • 0
    TI__Expert 4805 points

    Hi Maor,

    I think to start with, I would suggest referring to the PowerPoint below which explains how to achieve deterministic latency using JESD204B. The AFE devices use Subclass 1, and the PowerPoint does a good job at covering the sequence. Specially the figure in slide 13. JESD204C is very similar but the SYNC signals are no longer used.

    https://www.ti.com/lit/ug/snau140/snau140.pdf?ts=1731104008485&ref_url=https%253A%252F%252Fwww.google.com%252F

    After guaranteeing deterministic latency, there is one more step which is to make sure you are synchronizing the NCOs across multiple devices. Some of the common ways to do this are the following. 1st option being the easiest to do:

    1. If you can use an NCO frequency that is an integer multiple of SYSREF then that makes synchronizing the NCOs easier as this can be done through a regular bringup with the continuous SYSREF.
    2. If your NCO frequency is not an integer multiple of SYSREF you will be able to synchronize the NCOs with a SYSREF pulse if you are able to first DC couple your SYSREF.
    3. Otherwise, the only other option would be to use the SYSREF GPIO Latch where you must provide a signal that can reach all the AFEs that will be synchronized within one of the SYSREF periods such that they can mark the next SYSREF edge to synchronize to.

    Best,

    Camilo