Tool/software:
here i am trying the 1GHZ bandwidth latte script on ZCU102 FPGA board, while running that i got the below errors
And here is the code i am running.
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x1TX_42220; Data Rate = 983.04M
#In HSDC Pro ADC tab, Select AFE79xx_2x1RX_42220; Data Rate = 983.04M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
sysParams.RRFMode = 5 # RRF 0: 4T4R2F FDD Mode
sysParams.enableDacInterleavedMode=False
############## Digital Chain ##############
##### RX #####
sysParams.rxEnable = [True,False,True,False]
sysParams.ddcFactorRx = [2]*4 #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[9584.64,9500], #Band0, Band1 for RXA
[9584.64,9500], #Band0, Band1 for RXB
[9584.64,9500], #Band0, Band1 for RXC
[9584.64,9500]] #Band0, Band1 for RXD
##### FB #####
sysParams.ddcFactorFb = [3]*2 #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [9500,9500] #Band0 for FB1 and FB2
sysParams.fbEnable = [False,False]
##### TX #####
sysParams.txEnable = [False,True,False,True]
sysParams.ducFactorTx = [8]*4 #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
[9500,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
sysParams.txDataMux = [2,3,0,1,6,7,4,5]
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["42220"]*4
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["42220"]*4
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
############## LMK Params ##############
lmkParams.pllEn = True
lmkParams.inputClk = 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 368.64 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x0
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.initializeConfig()
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
And in some forums i saw that this " Los indicator for lane0" this kind of errors will because the LMFS settings that will differ on both LATTE AND FPGA side, but i am quite newbie in this domain, so i am not sure where exactly i need to check that LMFS settings in the TI_204c_IP or else in the GTH transceiver IP .I am attaching the code below. And please do suggest me to resolve the latte errors.
