ADS58J63: Questions about this device

Hello Jayden,

Please help advise the customer name and opportunity. I will ask our marketing team to reach out to you.

Jayden Qiu said:

1. How to configure the device to select which mode? Is the mode selection achieved by configuring the register through SPI communication?

The device is configured through SPI registers. The customer can use the EVM GUI to generate the configuration file

Jayden Qiu said:

2. Can I switch between normal mode and burst mode while the device is running? How to enable or switch to burst mode? How to trigger high-resolution sampling after switching to burst mode?

See datasheet section 7.4.7. There are auto mode and manual mode.

Jayden Qiu said:

3. Is the only difference between burst mode and normal mode in resolution? Will the frequency of the sampled digital signal transmitted to the FPGA change?

How does the customer define normal mode? There is no normal mode in the datasheet

In burst mode, there is low resolution (9-bit) and high resolution mode (14-bit) in the burst mode.

Below are all the modes available to this device

Jayden Qiu said:

4. In the typical circuit diagram in datasheet, CLKINP/CLKINM and SYSREFP/SYSREFM are both clocked by a clock generator. What is the general setting frequency of this external clock? Is there a recommended device for this clock? Can it be implemented by programming a fixed-frequency flip level using an IO port of the FPGA? What are the frequencies of CLKINP/CLKINM and SYSREFP/SYSREFM?

The datasheet discuss different recommendations based on different input scenarios. Please refer to section 7 in general.

Jayden Qiu said:

5. Is the 1.15V of IOVDD a built-in power supply of the device, or does it require an external 1.15V power supply? Can the 1.9V DVDD and AVDD be powered together?

IOVDD is externally supplied

Please see also section 8.2 and section 9. 

Please add some power filter for the DVDD and AVDD to increase RF and noise isolation between the two power supplies.

Jayden Qiu said:

6. Is SYNCbABP/SYNCbABM an IO port connected to the FPGA? How should this IO be configured? What do the 100 ohm and Vterm=1.2V marked in the typical circuit mean? What is the specific link from SYNCbABP/SYNCbABM to FPGA?

Yes, this is per JESD204B standard for LVDS based input configuration. See section 8.2 for typical connections. 

Adrian,

1. For the mode8-Burst mode, why there is 9-bit mode? What's the significance of this 9bit, since the ADC itself is 14bit?

In order for the ADS58J63 to meet export compliance regulation, we cannot enable the ADC to keep sending 14-bit. We have to have a lower resolution time frame for 9 bit in order to meet the total number of resolution bits for the export regulation.

Customers typically use mode 8 at 500MSPS. They only need to capture 14-bit mode momentarily, and do not need the whole time to operate at 14-bit. This is useful for DPD observation. 
2. I think customer is not talking about the trigger way, they want to change the device mode from anyone of mode1-7 to mode8 during working? Is it achievable?

Mode 1-7 have decimation enabled in order to limit the total amount of bandwidth to within TI and US export control rule. You must use bypass mode (mode 8) with burst mode to meet export control rule.
3. The CLKIN was use as the sampling rate of the ADC, so does it mean the CLKIN should be 500M?

The most preferred way to use this ADC is at 500MSPS