Tool/software:
I want to transfer JESD lanes 0-7 at a lane rate of 10Gbps.
For 8 lanes, I need a 256 wide bus. I want to achieve the proper mapping to construct the data samples to the DAC.
What is the sample order of the data on a 256 wide bus?
Latte settings
Fdac = 11796.48
LMFSHdTx = ['44210', '44210', '44210', '44210']
ducFactorTx = [24, 24, 24, 24]
