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AFE7950: 4T4R2F 8b10b 2.4576 Gbps Config not synchronizing

Jesse Hobart
Prodigy 10 points
Part Number: AFE7950

Tool/software:

Hello,

I had success bringing up the TI ZCU102 64b66b example design, and now I am attempting to bring up a JESD204B configuration using the AFE7950EVM connected to the Xilinx ZCU102 development board.  Here is my desired configuration:

JESD204B, 8b10b SERDES

4 Rx

2 Fb

4 Tx

ADC Fs   = 2949.12,  Decimate by 48

ADCFb Fs = 2949.12,  Decimate by 24

DAC Fs   = 11796.48, Interpolate by 96

SERDES rate = 2457.6

Use the AFE7950EVM on-board oscillator

I am building the TI204C-IP-Release-v1.12-LATEST/reference_designs/zcu102_8b10b design

I have done the following configuration to that design:

  1. pll_inst(sys_pll) settings: 
    1. input   =153.6 MHz
    2. clk_out1=153.6 MHz
    3. clk_out2=30.72 MHz -> mgt_freerun_clock
  2. xcvr_inst(gth_8b10b_xcvr) settings:
    1. Banks 129-130 utilized
    2. refclk=153.6 - Note: IP block says requested clock =156.25, actual clock 153.6
    3. refclk source = Bank130 MGTREFCLK0
    4. Free-running clock frequency = 30.72
  3. syncb pin settings (single-ended, locations chosen to match resistor population on stock AFE7950EVM).  The GPIO configuration in the script (attached) matches:
    1. set_property PACKAGE_PIN AE3 [get_ports adc_rx_sync_n]
    2. set_property IOSTANDARD LVCMOS18 [get_ports adc_rx_sync_n]
    3. set_property PACKAGE_PIN AF3 [get_ports dac_tx_sync_n]
    4. set_property IOSTANDARD LVCMOS18 [get_ports dac_tx_sync_n]
  4. Updates to jesd_link_params.vh to match configuration and ZCU102 SERDES mapping

Upon attempt to bring up design per TI204c-Setup.docx, I follow this order of operations:

  1. Power on ZCU102
  2. Power on AFE7950EVM
  3. Open Latte
  4. Run setup.py
  5. Run devInit.py
  6. Run 4T4R2F_2p4576.py
  7. Program FPGA
  8. Release master_reset_n -> 1
  9. Release tx_reset -> 0
  10. Run ConfigAfe.py
  11. Release rx_reset -> 0

Latte Log reports “Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.”

ILA shows notintable errors and disparity errors.  syncb signal is low, sysref is present, sysref realign is counting:

Both qpll0 instances report lock.  I added a vio to monitor sys_pll and sys_pll reports locked.

I have attempted to attach the relevant files.  Can anyone spot what might be causing the SERDES to not achieve synchronization?  Is there IP including Latte scripts that I could try that is known to be working in 8b10b mode in my setup (can be different sample rates/decimation, etc)?

2577.files.zip

  • 0
    Prodigy 10 points

    Update:

    I noticed that the 153.6 MHz reference clock was not exactly 153.6 MHz when measured with an oscilloscope, and I suspect that the multiply/divide ratios were not possible within the LMK device on the AFE7950EVM, so I updated this line in 

    4T4R2F_2p4576.py: setupParams.fpgaRefClk = 184.32 

    which is evenly divisible by the programmed lmkParams.inputClk = 1474.56

    I also updated the FPGA design to use 184.32 MHz as the MGTREFCLK and sys_pll.  

    Now the reference clocks and derived mgt_freerun_clk and sysref are the expected frequency when measured.

    This update results in a different set of messages in the Latte log:

    ...

    Sysref Read as expected

    ###########Device DAC JESD-RX 0 Link Status###########

    CS State TX0: 0b10101010 . It is expected to be 0b10101010

    FS State TX0: 0b00000000 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 0; Alarms: 0x0

    ###################################

    ###########Device DAC JESD-RX 1 Link Status###########

    CS State TX0: 0b10101010 . It is expected to be 0b10101010

    FS State TX0: 0b00000000 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 1; Alarms: 0x0

    ###################################

    AFE Configuration Complete

    AFE Setup is complete. Now follow these steps:

    1. Bring Rx out of reset
    2. Set rx_sync_reset_vio = 0, rx_lemc_to_buffer_release_delay[9:0] should change to a non-zero value
    3. Set up hw_ila_2 and view waveforms

    #================ ERRORS:2, WARNINGS:0 ===============#

    sys_pll and the two instances of qpll0 are locked, but the ILA in the FPGA shows rx_sync_n = 0.  notintable and disparity errors appear to be 0 now.

    This seems closer, but not yet synchronized.  Any thoughts as to what I can look at next would be appreciated.

  • 0 in reply to Jesse Hobart
    Prodigy 10 points

    Update:

    I updated 4T4R2F_2p4576.py to to enable single-ended LVCMOS sync:

    sysParams.jesdABLvdsSync= False

    sysParams.jesdCDLvdsSync= False

    Latte Log now shows different errors:

    Sysref Read as expected

    ###########Device DAC JESD-RX 0 Link Status###########

    lane0 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane1 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane2 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane3 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    CS State TX0: 0b00000000 . It is expected to be 0b10101010

    FS State TX0: 0b00000000 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 0; Alarms: 0xf0f0f0f00000000L

    ###################################

    ###########Device DAC JESD-RX 1 Link Status###########

    lane0 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane1 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane2 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    lane3 Errors=0b1111; Got errors: 8b/10b disparty error; 8b/10b not-in-table code error; code synchronization error; elastic buffer match error. The first no-/K/ does not match 'match_ctrl' and 'match_data' programmed values;

    CS State TX0: 0b00000000 . It is expected to be 0b10101010

    FS State TX0: 0b00000000 . It is expected to be 0b01010101

    Couldn't get the link up for device RX: 1; Alarms: 0xf0f0f0f00000000L

    FPGA ILA:

    files_update2.zip

  • 0 in reply to Jesse Hobart
    Prodigy 10 points

    Update:

    The version of jesd_link_params.vh that I started with in was incorrect for the ZCU102 board in the mapping and polarity of the GTH transceivers, so I had copied these lines from a difference reference design:

    `undef LANE_ADC_TO_GT_MAP

    `define LANE_ADC_TO_GT_MAP {3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0}

    `undef LANE_DAC_TO_GT_MAP

    `define LANE_DAC_TO_GT_MAP {3'd7,3'd6,3'd5,3'd4,3'd3,3'd2,3'd1,3'd0}

    and moved the lane assignments to: 

    `undef LANE_ADC_TO_GT_MAP

    `define LANE_ADC_TO_GT_MAP {3'd5,3'd4,3'd6,3'd7,3'd3,3'd0,3'd2,3'd1}

    `undef LANE_DAC_TO_GT_MAP

    `define LANE_DAC_TO_GT_MAP {3'd4,3'd5,3'd6,3'd7,3'd3,3'd0,3'd2,3'd1}

    It turns out that this version of the source code requires this assignment (a concatentation of integers) instead:

    `undef LANE_ADC_TO_GT_MAP

    `define LANE_ADC_TO_GT_MAP {5,4,6,7,3,0,2,1}

    `undef LANE_DAC_TO_GT_MAP

    `define LANE_DAC_TO_GT_MAP {4,5,6,7,3,0,2,1}

     Changing to a concatenation of integers, the JESD in my design now synchronizes.