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AFE7950: AFE7950 related

Salman Baig
Prodigy 20 points
Part Number: AFE7950

Tool/software:

Hi, 

We have developed JESD204 IP and testing it on KCU105 integrated with AFE7950.

1. AFE latte script shows AFE configuration complete and DAC JESD link status successful. We connected DAC output channel to signal analyser, signal spectrum was plotted.

2. In case of ADC JESD, K28.5 characters, ILAs, SYNC works fine, but lot of 8B10B errors are observed. Is this any config issue in Latte script or FPGA?

3. Also, we did loopback connection (DAC output channel to ADC input channel) using SMA cable, but no signal gets captured in ADC.

Kindly support us to resolve the issue.

regards

Salman

  • 0
    TI__Genius 14991 points

    Hi Salman,

    Can you share the exact errors you are seeing on the ADC JESD link? Also, can you confirm that the ADC JESD parameters match on both the ADC and FPGA sides? 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 20 points

    Hi David,

    1. We are seeing 8B:10B errors in all 8 channels of ADC. Couple of channels are having 1 in 100 while others have 1 in 1000. Higher error channels change in lane number every time we restart the system. 

    2. At the same time, DAC side seems to work perfect as per the status seen. AFE.adcDacSync() doesn't works as expected on DAC, but on ADC protocol wise it is correct, but 8B:10B remains same.

    3. We did connect DAC output to a Spectrum Analyser, the output spectrum is as expected [Around NCO frequency, our wave is seen]. But when we fed the same DAC output to ADC using a SMA cable, nothing is seen at the output of ADC.

    4. Tested on all ports of ADC, result is same. Even tried the sysParams.jesdLoopbackEn = 1, but no change.

    Let me repeat: K28.5, ILAS etc are received properly on all lanes, but we are seeing 8B:10B errors in receive + no output on ADC even in Data state.

    Also, JESD parameters on both ADC and FPGA are same. We tried with different configuration of LMFS, same 8B:10B errors found.

    regards

    Salman

  • 0 in reply to Salman Baig
    TI__Genius 14991 points

    Hi Salman,

    1. As mentioned in the previous response can you share the exact 8b10b errors that you are seeing. Without knowing which error you are seeing we are not able to provide much help. Also, is this seen on the TI204c IP reference design that was shared previously? 

    2. What you share what issue you are facing when running the AFE.adcDacSync function and is the AFE EVM being controlled through Latte? 

    3. If the ADC link is not up then you can expect there to be no data.

    4. The JESD loopback configuration would be used to test the AFE side only, as the ADC JESD data will be looped back to the DAC JESD. When in this mode you can feed in an input, from a signal generator, and then you should see an output of the DAC. 

    Regards,

    David Chaparro