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AFE7950: SYNC OUT

YuukiWatanabe
Prodigy 180 points
Part Number: AFE7950

Tool/software:

After the TX JESD link is up,
SYNC OUT repeatedly enables and disables.
It is not periodic (like a pulse).
There are no JESD errors on either the AFE or FPGA.
I will send you the Latte settings.
Could you help me identify where I am going wrong?

4774.Afe79xxPg1.txt

  • 0
    TI__Genius 17831 points

    Hi Yuuki,

    On the FPGA side are you using the Xilinx JESD IP or the TI JESD IP? Is this issue only seen on the TX jesd link or do you also see it on the Rx jesd link?

    One thing you can check is if your JESD IP is checking for the ILA data from each lane? 

    Regards,

    David Chaparro