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AFE7920: AFE7920 RX OUTPUT Problem

daesok Oh
Prodigy 10 points
Part Number: AFE7920

Tool/software:

Hi~

We designed with af7920 and xilinx xcku3p, and confirmed SYNC in JESD TX/RX.

In the above situation, it was confirmed that the CW signal was generated in the FPGA and output from the RFIC, but when the CW of SIG GEN. is applied to the RFIC input port, the corresponding SIGN wave is not monitored in the FPGA.

In order to verify JESD in the RFIC to FPGA path, when a RAMP pattern is generated in RFIC TX JESD, it is possible to check the situation in which the lamp pattern value is normally detected as shown in the 1-1 picture, but when CW is applied to the RFIC, only fine signals such as NOISE are captured as shown in Figure 1-2.

1-1

1-2

I hope you can explain the above situation, and please let me know what I need to check additionally.

  • 0
    TI__Guru* 78404 points

    Hello Mr. Oh,

    Please let us know if you have enabled the RXTDD function to ensure the RX ADC chain are enabled and powered-up.

    I believe Aman and Mirana on working with JH from Arrow offline on this. Please let us know if you have received the answers from JH from Arrow.

    -Kang

  • 0 in reply to Kang Hsia
    Prodigy 10 points

    i already checked the RXTDD signal to enable the RX ADC.

    for now, RF input signal can be monitored at FPGA JESD RX data. but the data signals are attenuated and has some phase noise.
    Anyway i've been receiving answers from JH in Arrow.

    thanks.