AFE7950EVM: SPI read polling error

Hi Ajay,

Was this setup tested using the AFE79xx GUI before updating the board for SPI through FMC? The errors that you are seeing are DAC JESD related. One of them is saying that the SYNC signal is not reaching the FPGA from the DAC as the JESD IP is not sending the K character to the DAC.

If you probe the SYNC signal do you see it go low and then back high? 

Regards,

David Chaparro 

Hi David,

As you mentioned the tx sync signal go low and high. I shared my ILA screenshot which indicate there is problem in tx sync signal.

May i know how to resolve it and what is causing this problem.

Hi Ajay,

The JESD error that you are seeing indicates that the DAC is not receiving the K character from the FPGA. Can you please check the following? 

1. For the DAC Sync signal, do you only see it transition from High>Low>High one time or does this continue to happen?
   
2. The JESD parameters on the AFE and FPGA should match. Can you confirm that JESD settings match on both? 
3. Was the setup first tested using the AFE79xx GUI programming the EVM?

Do you see any errors on the ADC JESD link, which would be reported on the FPGA side? 

Regards,

David Chaparro 

Hi David,

1 : Only DAC sync signal observing transition High>Low>High continuously. Sometimes it is high for longer time also.

2 : Since we did the parameter check through Latte once after the working of it we try doing it with our application the same parameter settings in AFE and FPGA.

3 : Yes initially it has been tested using Latte then we started proceeding with our application.

From latte we converted the SPI configuration for both LMK and AFE to txt file and used the SPI api calls in our application.

Hi Ajay,

Can you share both the Latte script and the configuration file that you are using on your setup? 

Regards,

David Chaparro 

## Initiates AFE79xx Bring-up
setupParams.skipLmk	=	True
AFE.deviceBringup()

AFE.TOP.overrideTdd(15,3,15)

#fpgaside 24410 afeside 12410 1 inst's are there
##############		Read me			##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 245.76M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 245.76M ---> To capture 4 RX channels

sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion

setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro 
##############		Top Level			##############
sysParams.FRef			= 491.52
sysParams.FadcRx		= 2949.12
sysParams.FadcFb		= 2949.12
sysParams.Fdac			= 2949.12*4
sysParams.externalClockRx=False
sysParams.externalClockTx=False
													
##############		Digital Chain		##############

		#####	RX	#####
sysParams.ddcFactorRx	=	[12,12,12,12]			#DDC decimation factor for RX A, B, C and D
sysParams.rxEnable		=   [True,True,False,False]
sysParams.rxNco0		= 	[[1500,1500],			#Band0, Band1 for RXA 
							[1500,1500],        	#Band0, Band1 for RXB 
							[1500,1500],        	#Band0, Band1 for RXC 
							[1500,1500]]        	#Band0, Band1 for RXD  

		#####	FB	#####
sysParams.fbEnable		=	[False,False]
sysParams.ddcFactorFb	=	[12,12]					#DDC decimation factor for FB 1 and 2
sysParams.fbNco0		= 	[9500,9500]				#Band0 for FB1 and FB2 

		#####	TX	#####
sysParams.ducFactorTx	=	[48,48,48,48]			#DUC interpolation factor for TX A, B, C and D
sysParams.txEnable		=   [True,True,False,False]
sysParams.txNco0		= 	[[1500,1500],			#Band0, Band1 for TXA 
							[1500,1500],        	#Band0, Band1 for TXB 
							[1500,1500],        	#Band0, Band1 for TXC 
							[1500,1500]]        	#Band0, Band1 for TXD


##############		JESD		##############

		#####	ADC-JESD	#####
sysParams.jesdSystemMode= [3,3]
													#SystemMode 0:	2R1F-FDD						; rx1-rx2-fb -fb
													#SystemMode 1:	1R1F-FDD						; rx -rx -fb -fb
													#SystemMode 2:	2R-FDD							; rx1-rx1-rx2-rx2
													#SystemMode 3:	1R								; rx -rx -rx -rx
													#SystemMode 4:	1F								; fb -fb- fb -fb
													#SystemMode 5:	1R1F-TDD						; rx/fb-rx/fb-rx/fb-rx/fb
													
sysParams.jesdTxProtocol= [0,0]						# 0 - 8b/10b encoding; 2 - 64b/66b encoding 
sysParams.LMFSHdRx		= ["24410","24410","24410","24410"]   #changed by Lakshmi ["44210","44210","44210","44210"] 
													# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
													# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb		= ["24410","24410"]

sysParams.rxJesdTxScr	= [True,True,True,True] 
sysParams.fbJesdTxScr	= [True,True]

sysParams.rxJesdTxK		= [16,16,16,16]
sysParams.fbJesdTxK		= [16,16]

sysParams.jesdTxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location. 
													# For example, if you want to exchange the first two lines of each 2T,
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.serdesTxLanePolarity = [1,1,0,0,0,0,0,0]	########## newly added
sysParams.jesdTxRbd		= [2, 2] 					########## newly added
		#####	DAC-JESD	#####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx		= ["24410","24410","24410","24410"]  
sysParams.jesdRxLaneMux	= [0,1,2,3,4,5,6,7]			# Enter which lanes you want in each location.
sysParams.serdesRxLanePolarity = [1,1,0,0,0,0,0,0]													# For example, if you want to exchange the first two lines of each 2R
													#		this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd		= [2, 2] 					########## changed
sysParams.jesdRxScr		= [True,True,True,True]
sysParams.jesdRxK		= [16,16,16,16]

		#####	JESD Common	#####
	
sysParams.jesdABLvdsSync= False
sysParams.jesdCDLvdsSync= False
sysParams.syncLoopBack	= True	#JESD Sync signal is connected to FPGA

##############		GPIO		##############
sysParams.gpioMapping	= {
						'H8': 'ADC_SYNC0',
						'H7': 'DAC_SYNC0',  	#'ADC_SYNC1',
						'N8': 'ADC_SYNC2',
						'N7': 'ADC_SYNC3',
						'H9': 'ADC_SYNC1',		#'DAC_SYNC0',
						'G9': 'DAC_SYNC1',
						'N9': 'DAC_SYNC2',
						'P9': 'DAC_SYNC3',
						'P14': 'GLOBAL_PDN',
						'K14': 'FBABTDD',
						'R6': 'FBCDTDD',
						'H15': ['TXATDD','TXBTDD'],
						'V5': ['TXCTDD','TXDTDD'],
						'E7': ['RXATDD','RXBTDD'],
						'R15': ['RXCTDD','RXDTDD']}

##############		LMK Params		##############
lmkParams.pllEn			= True
lmkParams.inputClk		= 983.04 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk	= True
setupParams.fpgaRefClk	= 245.76 # Should be equal to LaneRate/40 for TSW14J56

##############		Logging		##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1

device.delay_time = 0
#--------------------------------------#
setupParams.skipLmk	=	False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = False
AFE.LMK.lmkConfig()

here i am attaching the cpp file which contains the functions and the code to configure the AFE chip, the sequence is same as latte the SPI reads/writes have been taken as reference from the .txt file generated from latte script after configuring the AFE namely "Afe79xxPg1Format5C.txt" and Afe79xxPg1.txt   Afe79xxPg1Format5C.txt

//LMK04828
SPIWrite 0000,80,0,7
SPIWrite 0000,00,0,7
SPIWrite 0000,80,0,7
SPIWrite 0000,00,0,7
SPIWrite 0000,80,0,7
SPIWrite 0000,00,0,7
SPIWrite 014a,03,0,7
SPIWrite 014a,33,0,7
SPIWrite 0000,00,0,7
SPIWrite 0002,00,0,7
SPIWrite 0100,0c,0,7
SPIWrite 0100,0c,0,7
SPIWrite 0100,0c,0,7
SPIWrite 0101,55,0,7
SPIWrite 0101,55,0,7
SPIWrite 0103,01,0,7
SPIWrite 0103,01,0,7
SPIWrite 0103,01,0,7
SPIWrite 0104,00,0,7
SPIWrite 0104,00,0,7
SPIWrite 0104,20,0,7
SPIWrite 0104,20,0,7
SPIWrite 0105,00,0,7
SPIWrite 0105,00,0,7
SPIWrite 0106,18,0,7
SPIWrite 0106,18,0,7
SPIWrite 0106,10,0,7
SPIWrite 0106,10,0,7
SPIWrite 0106,90,0,7
SPIWrite 0106,f0,0,7
SPIWrite 0107,01,0,7
SPIWrite 0107,01,0,7
SPIWrite 0107,11,0,7
SPIWrite 0107,11,0,7
SPIWrite 0108,06,0,7
SPIWrite 0108,26,0,7
SPIWrite 0108,66,0,7
SPIWrite 0109,55,0,7
SPIWrite 0109,55,0,7
SPIWrite 010b,01,0,7
SPIWrite 010b,01,0,7
SPIWrite 010b,01,0,7
SPIWrite 010c,00,0,7
SPIWrite 010c,00,0,7
SPIWrite 010c,20,0,7
SPIWrite 010c,20,0,7
SPIWrite 010d,00,0,7
SPIWrite 010d,00,0,7
SPIWrite 010e,18,0,7
SPIWrite 010e,18,0,7
SPIWrite 010e,10,0,7
SPIWrite 010e,10,0,7
SPIWrite 010e,90,0,7
SPIWrite 010e,f0,0,7
SPIWrite 010f,04,0,7
SPIWrite 010f,04,0,7
SPIWrite 010f,14,0,7
SPIWrite 010f,14,0,7
SPIWrite 0110,08,0,7
SPIWrite 0110,08,0,7
SPIWrite 0110,08,0,7
SPIWrite 0111,55,0,7
SPIWrite 0111,55,0,7
SPIWrite 0113,00,0,7
SPIWrite 0113,00,0,7
SPIWrite 0113,00,0,7
SPIWrite 0114,00,0,7
SPIWrite 0114,00,0,7
SPIWrite 0114,00,0,7
SPIWrite 0114,00,0,7
SPIWrite 0115,00,0,7
SPIWrite 0115,00,0,7
SPIWrite 0116,11,0,7
SPIWrite 0116,11,0,7
SPIWrite 0116,19,0,7
SPIWrite 0116,19,0,7
SPIWrite 0116,99,0,7
SPIWrite 0116,f9,0,7
SPIWrite 0117,00,0,7
SPIWrite 0117,00,0,7
SPIWrite 0117,00,0,7
SPIWrite 0117,00,0,7
SPIWrite 0118,18,0,7
SPIWrite 0118,18,0,7
SPIWrite 0118,18,0,7
SPIWrite 0119,55,0,7
SPIWrite 0119,55,0,7
SPIWrite 011b,00,0,7
SPIWrite 011b,00,0,7
SPIWrite 011b,00,0,7
SPIWrite 011c,00,0,7
SPIWrite 011c,00,0,7
SPIWrite 011c,20,0,7
SPIWrite 011c,20,0,7
SPIWrite 011d,00,0,7
SPIWrite 011d,00,0,7
SPIWrite 011e,11,0,7
SPIWrite 011e,11,0,7
SPIWrite 011e,19,0,7
SPIWrite 011e,19,0,7
SPIWrite 011e,99,0,7
SPIWrite 011e,f9,0,7
SPIWrite 011f,00,0,7
SPIWrite 011f,00,0,7
SPIWrite 011f,00,0,7
SPIWrite 011f,00,0,7
SPIWrite 0120,0c,0,7
SPIWrite 0120,0c,0,7
SPIWrite 0120,0c,0,7
SPIWrite 0121,55,0,7
SPIWrite 0121,55,0,7
SPIWrite 0123,00,0,7
SPIWrite 0123,00,0,7
SPIWrite 0123,00,0,7
SPIWrite 0124,00,0,7
SPIWrite 0124,00,0,7
SPIWrite 0124,00,0,7
SPIWrite 0124,00,0,7
SPIWrite 0125,00,0,7
SPIWrite 0125,00,0,7
SPIWrite 0126,11,0,7
SPIWrite 0126,11,0,7
SPIWrite 0126,19,0,7
SPIWrite 0126,19,0,7
SPIWrite 0126,99,0,7
SPIWrite 0126,f9,0,7
SPIWrite 0127,01,0,7
SPIWrite 0127,01,0,7
SPIWrite 0127,11,0,7
SPIWrite 0127,11,0,7
SPIWrite 0128,08,0,7
SPIWrite 0128,08,0,7
SPIWrite 0128,08,0,7
SPIWrite 0129,55,0,7
SPIWrite 0129,55,0,7
SPIWrite 012b,00,0,7
SPIWrite 012b,00,0,7
SPIWrite 012b,00,0,7
SPIWrite 012c,00,0,7
SPIWrite 012c,00,0,7
SPIWrite 012c,00,0,7
SPIWrite 012c,00,0,7
SPIWrite 012d,00,0,7
SPIWrite 012d,00,0,7
SPIWrite 012e,11,0,7
SPIWrite 012e,11,0,7
SPIWrite 012e,19,0,7
SPIWrite 012e,19,0,7
SPIWrite 012e,99,0,7
SPIWrite 012e,f9,0,7
SPIWrite 012f,00,0,7
SPIWrite 012f,00,0,7
SPIWrite 012f,00,0,7
SPIWrite 012f,00,0,7
SPIWrite 0130,0c,0,7
SPIWrite 0130,0c,0,7
SPIWrite 0130,0c,0,7
SPIWrite 0131,55,0,7
SPIWrite 0131,55,0,7
SPIWrite 0133,01,0,7
SPIWrite 0133,01,0,7
SPIWrite 0134,00,0,7
SPIWrite 0134,00,0,7
SPIWrite 0134,20,0,7
SPIWrite 0134,20,0,7
SPIWrite 0135,00,0,7
SPIWrite 0135,00,0,7
SPIWrite 0136,19,0,7
SPIWrite 0136,19,0,7
SPIWrite 0136,11,0,7
SPIWrite 0136,11,0,7
SPIWrite 0136,91,0,7
SPIWrite 0136,f1,0,7
SPIWrite 0137,01,0,7
SPIWrite 0137,01,0,7
SPIWrite 0137,01,0,7
SPIWrite 0137,01,0,7
SPIWrite 0138,00,0,7
SPIWrite 0138,00,0,7
SPIWrite 0138,20,0,7
SPIWrite 0139,03,0,7
SPIWrite 0139,03,0,7
SPIWrite 013b,00,0,7
SPIWrite 013a,03,0,7
SPIWrite 013d,08,0,7
SPIWrite 013c,00,0,7
SPIWrite 013e,03,0,7
SPIWrite 013f,00,0,7
SPIWrite 013f,00,0,7
SPIWrite 013f,00,0,7
SPIWrite 013f,00,0,7
SPIWrite 0140,06,0,7
SPIWrite 0140,04,0,7
SPIWrite 0140,00,0,7
SPIWrite 0140,00,0,7
SPIWrite 0140,00,0,7
SPIWrite 0140,00,0,7
SPIWrite 0140,00,0,7
SPIWrite 0140,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0141,00,0,7
SPIWrite 0142,00,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,92,0,7
SPIWrite 0143,12,0,7
SPIWrite 0144,01,0,7
SPIWrite 0144,03,0,7
SPIWrite 0144,07,0,7
SPIWrite 0144,0f,0,7
SPIWrite 0144,1f,0,7
SPIWrite 0144,3f,0,7
SPIWrite 0144,7f,0,7
SPIWrite 0144,ff,0,7
SPIWrite 0146,18,0,7
SPIWrite 0146,18,0,7
SPIWrite 0146,18,0,7
SPIWrite 0146,10,0,7
SPIWrite 0146,10,0,7
SPIWrite 0146,10,0,7
SPIWrite 0147,3a,0,7
SPIWrite 0147,3a,0,7
SPIWrite 0147,1a,0,7
SPIWrite 0147,1a,0,7
SPIWrite 0148,02,0,7
SPIWrite 0148,02,0,7
SPIWrite 0149,42,0,7
SPIWrite 0149,42,0,7
SPIWrite 0149,42,0,7
SPIWrite 014c,00,0,7
SPIWrite 014b,16,0,7
SPIWrite 014b,16,0,7
SPIWrite 014b,16,0,7
SPIWrite 014b,16,0,7
SPIWrite 014b,16,0,7
SPIWrite 014b,16,0,7
SPIWrite 014d,00,0,7
SPIWrite 014e,00,0,7
SPIWrite 014e,c0,0,7
SPIWrite 014f,7f,0,7
SPIWrite 0150,03,0,7
SPIWrite 0150,03,0,7
SPIWrite 0150,03,0,7
SPIWrite 0150,03,0,7
SPIWrite 0150,03,0,7
SPIWrite 0150,43,0,7
SPIWrite 0152,00,0,7
SPIWrite 0151,02,0,7
SPIWrite 0154,78,0,7
SPIWrite 0153,00,0,7
SPIWrite 0156,7d,0,7
SPIWrite 0155,00,0,7
SPIWrite 0158,96,0,7
SPIWrite 0157,00,0,7
SPIWrite 015a,00,0,7
SPIWrite 0159,06,0,7
SPIWrite 015b,d4,0,7
SPIWrite 015b,d4,0,7
SPIWrite 015b,d4,0,7
SPIWrite 015b,d4,0,7
SPIWrite 015d,00,0,7
SPIWrite 015c,20,0,7
SPIWrite 015e,00,0,7
SPIWrite 015e,00,0,7
SPIWrite 015f,0b,0,7
SPIWrite 015f,0b,0,7
SPIWrite 0161,01,0,7
SPIWrite 0160,00,0,7
SPIWrite 0162,5c,0,7
SPIWrite 0162,5c,0,7
SPIWrite 0162,44,0,7
SPIWrite 0162,44,0,7
SPIWrite 0165,0c,0,7
SPIWrite 0164,00,0,7
SPIWrite 0163,00,0,7
SPIWrite 0166,00,0,7
SPIWrite 0168,0c,0,7
SPIWrite 0167,00,0,7
SPIWrite 0166,00,0,7
SPIWrite 0169,59,0,7
SPIWrite 0169,59,0,7
SPIWrite 0169,59,0,7
SPIWrite 0169,59,0,7
SPIWrite 0169,59,0,7
SPIWrite 016b,00,0,7
SPIWrite 016a,20,0,7
SPIWrite 016c,00,0,7
SPIWrite 016c,00,0,7
SPIWrite 016d,00,0,7
SPIWrite 016d,00,0,7
SPIWrite 016e,13,0,7
SPIWrite 016e,13,0,7
SPIWrite 017c,15,0,7
SPIWrite 017d,0f,0,7
SPIWrite 0143,51,0,7
SPIWrite 0139,00,0,7
SPIWrite 0144,3c,0,7
SPIWrite 0143,71,0,7
SPIWrite 0143,51,0,7
SPIWrite 0144,ff,0,7
SPIWrite 0139,00,0,7
SPIWrite 0139,03,0,7

Hi Ajay,

Thank you for sharing these files. I do not see any specific issue with the files. 

Common issues that we have seen cause the sync to toggle are given below. Can you check these on your setup?

1. SYSREF being turned off or not the correct frequency. 
   
   1. Can you probe and check that the SYSREF is on and running.
2. JESD link parameters are do not match. Is the K parameter set to the same value on both sides? 

You mentioned that you have tested this using the Latte software to control the EVM. When doing this did you use the same FW on the FPGA that you are using now. If not, what changes were made from then to now? 

Were you able to check if the ADC JESD link was up and if it had any errors? 

Regards,

David Chaparro

1. This is the SYSREF input to the FPGA which i probed in the ILA of vivado tool.

2. JESD parameters are same and the K value is also same which is 16 in both latte as well as our configuration.

3.ADC link looks stable not toggling.

The only change when configuring from latte to our current setup is, now we are configuring LMK and AFE through SPI and the JESD cores from the  Processing system (ARM processor) on our SOC and the FPGA remains  same in both cases

Hi David,

We observed when we check the signals in our debug tool ILA vivado tool. TX_SYNC is not toggling. But still we are getting the SPI read polling error already mentioned in the above screenshot while configuring AFE7950 EVM.

Regards,

Ajay tj

Hi Ajay,

Just to confirm, you are now seeing the tx_sync signal only go from high->low->high one time, but get the initial errors you mentioned in the post? 

Are you able to see the reset signals toggle as expected? I wonder if the resets are not being disserted which can cease the issue you are seeing. 

Regards,

David Chaparro

Hi David,

Yes tx_sync signal only go from high->low->high one time. Still getting the initial errors mentioned in the post.

The Reset sequence we are following is :

Hi David,

Since we are able to see the tx and rx sync high, can you help us how to generate test pattern for AFE7950 ADC using SPI write. Which is the address to set it generate.

Regards,

Ajay tj