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AFE7950EVM: TRF1208-AFE7950EVM

Kenan Canko
Prodigy 30 points
Part Number: AFE7950EVM
Other Parts Discussed in Thread: AFE7950

Tool/software: 

#======
#Executing .. AFE7950/bringup/setup.py
#Start Time 2025-03-26 09:50:32.822000 
AFE79xxLibraryPG1p0
spi - USB Instrument created.
resetDevice
Kintex RegProgrammer - USB Instrument created.
Kintex RegProgrammer - USB Instrument created.
#Done executing .. AFE7950/bringup/setup.py
#End Time 2025-03-26 09:50:37.933000
#Execution Time = 5.11100006104 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/devInit.py
#Start Time 2025-03-26 09:50:43.237000 
Power Card - USB Instrument created.
Reset the FPGA and try again.
Loaded Libraries
Refreshed GUI
#Done executing .. AFE7950/bringup/devInit.py
#End Time 2025-03-26 09:51:30.069000
#Execution Time = 46.8320000172 s 
#================ ERRORS:0, WARNINGS:1 ================#
#======
#Executing .. AFE7950/bringup/TI_IP_12Gbps_8Lane_ConfigLmk.py
#Start Time 2025-03-26 09:51:38.173000 
The External Sysref Frequency should be an integer factor of: 1.92MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
LMK Clock Divider - Device registers reset.
LMK Clock Divider - Device registers reset.
REFCLOCK is used from LMK source, ensure board connections are ok to do the same
#Done executing .. AFE7950/bringup/TI_IP_12Gbps_8Lane_ConfigLmk.py
#End Time 2025-03-26 09:51:39.110000
#Execution Time = 0.936999797821 s 
#================ ERRORS:0, WARNINGS:1 ================#
#======
#Executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#Start Time 2025-03-26 09:54:39.673000 
The External Sysref Frequency should be an integer factor of: 1.92MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 15
Setting RBD to: 15
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0x0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x0
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#End Time 2025-03-26 09:56:16.572000
#Execution Time = 96.8989999294 s 
#================ ERRORS:2, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#Start Time 2025-03-26 10:01:54.822000 
The External Sysref Frequency should be an integer factor of: 1.92MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 15
Setting RBD to: 15
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0x0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x0
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#End Time 2025-03-26 10:03:31.620000
#Execution Time = 96.7979998589 s 
#================ ERRORS:2, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/TI_IP_12Gbps_8Lane_ConfigLmk.py
#Start Time 2025-03-26 10:12:11.344000 
The External Sysref Frequency should be an integer factor of: 1.92MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
#Done executing .. AFE7950/bringup/TI_IP_12Gbps_8Lane_ConfigLmk.py
#End Time 2025-03-26 10:12:11.441000
#Execution Time = 0.0969998836517 s 
#================ ERRORS:0, WARNINGS:0 ================#
#======
#Executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#Start Time 2025-03-26 10:13:19.056000 
The External Sysref Frequency should be an integer factor of: 1.92MHz
2T2R1F Number: 0
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
2T2R1F Number: 1
Valid Configuration: True
laneRateRx: 12165.12
laneRateFb: 12165.12
laneRateTx: 12165.12
LMK and FPGA Configured.
DONOT_OPEN_Atharv_FULL - Device registers reset.
chipType: 0xa
chipId: 0x78
chipVersion: 0x11
AFE Reset Done
Fuse farm load autoload done successful
No autload error
Fuse farm load autoload done successful
No autload error
AFE MCU Wake up done and patch loaded.
PLL Locked
AFE PLL Configured.
AFE SerDes Configured.
AFE Digital Chains configured.
AFE TX Analog configured.
AFE RX Analog configured.
AFE FB Analog configured.
AFE JESD configured.
AFE AGC configured.
AFE GPIO configured.
Sysref Read as expected
Setting RBD to: 15
Setting RBD to: 15
###########Device DAC JESD-RX 0 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 0; Alarms: 0x0
###################################
###########Device DAC JESD-RX 1 Link Status###########
CS State TX0: 0b00000000 . It is expected to be 0b10101010
BUF State TX0: 0b01010101 . It is expected to be 0b11111111
Couldn't get the link up for device RX: 1; Alarms: 0x0
###################################
AFE Configuration Complete
#Done executing .. AFE7950/bringup/TI_IP_ConfigAfe.py
#End Time 2025-03-26 10:14:57.897000
#Execution Time = 98.8410000801 s 
#================ ERRORS:2, WARNINGS:0 ================#

We are trying to use TRF1208-AFE7950EVM board with our iW-RainboW-G35M-11 SoM and iWave DevKit but we are gitting the error that you can see Latte's log . Can you help us? 

  • 0
    TI__Genius 17831 points

    Hi Kenan,

    Were any changes made to the AFE script? If so can you share the changes made.

    On the FPGA side, can you share which reference design you used as a starting point? Were any updates made to the JESD settings such as the Lane Polarity settings, which could cause link issues?

    The issues that we see are for the DAC JESD link. Have you tested the ADC link by setting the 'rx_sync_reset_vio' signal to '0' and checking if the 'rx_lemc_to_buffer_release_delay' signal gives an output that is not '0'?

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Hello David,

    We used ZCU102_AFE79xx_64b66b_12Gbps design as a starting point, we change the gth_64b66b_xcvr ip from GTH to GTY, we reconfigure the pins corresponding to old ip core that you made in gth_64b66b_xcvr. We change the constraint.xdc file with  iW-RainboW-G35M-11 SoM pins then we get some clock pin error about refclk_p we add 
    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets TI_IP_inst/jesd_ip_gen.j64b66b_inst/xcvr_gen.xcvr_inst/gt_refclk0_buf]
    set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets IBUFGDS_inst/O]
    This rules and we changed pll ip cores inputs as a global buffer and its outputs as a BUFG then we succesfully write bitsream and we get these errors.

    when we change rx_sync_reset_vio there is no change in rx_lemc_to_buffer_release_delay.

    Thank you

  • 0 in reply to Kenan Canko
    TI__Genius 17831 points

    Hi Kenan,

    When moving over from the ZCU design were any update made to the mode of operation on the AFE? 

    Also, can you share a screen shot of the transceiver wizard page? 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Hi David,
    We did not touch Latte codes so that no we did not have any update on AFE side.

  • 0 in reply to Kenan Canko
    TI__Genius 17831 points

    Hi Kenan,

    Can you report the current consumption of the AFE EVM after running the ConfigAfe script? Also, one thing that could cause issues like this would be the sysref and core clock to the FPGA. Can you confirm that the constraints for the core clock and sysref, which are on pins G6/G7 and G9/G10, were updated as needed? 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Hello David,

    Firstly, thank you so much for your effort. The power consumption is 3.141A at 5.5V and I'm adding the ILA screenshots about sysref clock can you check please?

  • 0 in reply to Kenan Canko
    TI__Genius 17831 points

    Hi Kenan,

    One thing that you can also look at is the SerDes lane polarities. Are there any specific lanes that are inverted on this dev kit? The reference designs has specific lanes inverted based on the connection of the AFE EVM to the ZCU102.

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 30 points

    Hello David, I checked what you said but there is not a issue about lane polarities but I found a strange thing, in AFE7950 JESD Core Clock pins goes to FMC connector's G6, G7 pins but when I checked the iWave schematics FMC+ connector's G6,G7 pins are connected DBC pin not GC so that we can not use the core clock (in FMC connector we got another issue btw.). Do you have any solution for that?

    Thank you David.