AFE7950-SP: Reg - Clock and SYSREF path in AFE7950

Tool/software:

Dear team,

I am using LMK04832 for sourcing clock to AFE7950.I am having only one ADC chip in my module.

Clock and SYSREF is generated from LMK04832 .Length matching for Clock path and  SYSREF path is done in our PCB .

What is the purpose  for length matching the clock and SYSREF lines ,If length match between the CLOCK and SYSREF is not done what will happen?

With reference to the above question, Main Clock and the SYSREF can route in same layer? if No what is the reason