AFE7950: How to synchronize multiple AFEs

Tool/software:

We are currently evaluating a system using approximately 40 AFE7950 devices. We are considering how to synchronize the phases of all channels in a practical manner when the actual devices are manufactured.

We plan to use JESD 204B Subclass 1 for data transfer with the FPGA, and based on my understanding, the following two requirements must be strictly adhered to:

1. Strictly adhere to the device clock and SYSREF setup/hold time specifications

2. Distribute the device clock and SYSREF to all AFEs at the same time

We are considering adjusting the phase as follows to address these two points. Is this correct? If there is a more efficient way to adjust the phase, please advise.

For 1

AFE79xx has a SYSREF timing detector, so we plan to monitor the detection results via SPI and use the phase adjustment function of a clock buffer such as LMX1205 to optimize the phase between the device clock and SYSREF.

(Is this SYSREF timing detector included in all AFE79xx devices? As far as I can tell, it is only mentioned in the AFE7906 datasheet.)

For 2

After performing 1, monitor the SYSREF of each AFE using an oscilloscope and use the phase adjustment function of a clock buffer like the LMX1205 to adjust the device clock and SYSREF by the same amount.(Since the device clock frequency is high, I believe it is better to monitor the SYSREF.)