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AFE7950EVM: AFE7950EVM: Regarding the error message that occurred while running the ZCU102_AFE79xx_64b66b_12 Gbps example.

Part Number: AFE7950EVM

Tool/software:

Hello,

We are working with the ZCU102_AFE79xx_64b66b_12 Gbps example.

While following the TI JESD204C-Setup Guide, we ran into a problem.

In Latte script mode, setup.py, devInit.py, and TI_IP_12Gbps_8Lane_ConfigLmk.py all executed correctly.
However, when we run TI_IP_ConfigAfe.py (page 7 of the guide), we get the following errors instead of the expected output:


###########Device DAC JESD-RX 0 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
Serdes-FIFO error for lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Serdes-FIFO error for lane 1: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 0; Alarms: 0x3300
###################################
###########Device DAC JESD-RX 1 Link Status###########
LOS Indicator for (Serdes Loss of signal) lane 0: 1
LOS Indicator for (Serdes Loss of signal) lane 1: 1
Comma Align Lock Lane0: False; Please check if the transmitter is sending data and eye is good.
Comma Align Lock Lane1: False; Please check if the transmitter is sending data and eye is good.
CS State TX0: 0b00000000 . It is expected to be 0b00001010
FS State TX0: 0b00000000 . It is expected to be 0b00000101
Couldn't get the link up for device RX: 1; Alarms: 0x300
###################################
AFE Configuration Complete
#Done executing .. AFE79xx/bringup/TI_IP_ConfigAfe.py
#End Time 2025-07-03 16:51:31.663000
#Execution Time = 116.259000063 s
#================ ERRORS:12, WARNINGS:0 ================#


Could you provide advice on how to resolve this error?

Thank you.

  • Hi Sanghyun,

    The errors that you are seeing are pointing to an issue on the FPGA side. Can you confirm that you are connected to the correct FMC connector on the ZCU102 and released the FPGA resets as covered in the setup guide?

    Specifically this error can occur when the master_reset_n or tx_sync_reset were not released on the FPGA side before configuring the AFE. 

    Regards,

    David Chaparro