AFE7900EVM: High Latency Observed in JESD204 Loopback Test with ZCU102 + AFE7900EVM

Sangcheol Lee

Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900

Tool/software:

Hi ,

I’m currently testing the TI JESD204 IP on a Xilinx ZCU102 board connected to an AFE7900EVM.
To build the Vivado project, I used:

The ZCU102_AFE79xx_8b10b_10Gbps Latte script example

The reference design files from TI204C-IP-Release-v1.11-LATEST/reference_designs/zcu102_8b10b

The setup uses Vivado 2021.2 and TI JESD204C IP version 1.11.

To evaluate latency, I performed a loopback test by routing the JESD204 Rx input lane directly to the Tx output lane within the TI_204c_IP_ref.sv file, as shown below:

<modified code>
assign tx_lane_data = (enable_loopback) ? rx_lane_data : tx_lane_data_sine;

I applied a 5G, 100 MHz NR signal to the RxB input port (J1) and measured the corresponding delay at the TxB output port (J7).
The measured total latency is approximately 17.5 µs as shown below figure, which seems excessively high—even accounting for the digital filtering stages in the AFE7900 DDC/DUC paths.

Could you help me understand what might be contributing to this large latency during the loopback test?
My goal is to reduce the total latency to less than 1 µs.

Do you have any recommendations for optimizing latency when using the TI JESD204 IP with the AFE7900?

Any guidance or insights would be greatly appreciated.

Thank you!

-- Sangcheol

5 months ago

0 Sangcheol Lee 5 months ago

Prodigy 40 points

Hi,

I wanted to share an update regarding the latency issue I previously reported.

After updating to TI JESD204C IP v1.12 and migrating to Vivado 2023.2, the loopback latency issue appears to be resolved. In particular, when comparing the synthesis reports:

Under Vivado 2021.2, the implementation shows 4 BRAMs used per JESD Tx lane.
In contrast, Vivado 2023.2 shows no BRAMs used, even though the source code remains identical.
(Please refer to attached Fig. 1 and Fig. 2.)

This suggests that the BRAM-based retiming buffers used in earlier Vivado builds may have contributed to the increased latency in the Tx path.

With the updated toolchain and IP version, the JESD Tx path appears to be more optimized.

As a result, the measured loopback latency (from RF Rx port to Tx port) is now approximately 1.1 µs, a significant improvement. (See Fig. 3 for measurement.)

Thank you for your continued support.

Best regards,

-- Sangcheol

Fig 1. Vivado 2021.2 utilization report

Fig 2. Vivado 2023.2 utilization report

Fig 3. loopback delay RFin -> RF out

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AFE7900EVM: High Latency Observed in JESD204 Loopback Test with ZCU102 + AFE7900EVM