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AFE7900EVM: AFE7903

Satya Srujan Akkineni
Prodigy 10 points
Part Number: AFE7900EVM
Other Parts Discussed in Thread: AFE7900

Tool/software:

Hi, 

I would like to integrate ZCU102 evaluation board with AFE7900 EVM. I want SPI to be configured so that I can establish communication with the transceiver through Vitis. I should use JESD for data transfer between PL and transceiver. I want the SPI to be initialised from the Zynq Ultrascale+ MPSoC. Also, the JESD ip provided is in .sv or .svp format. I want it to be in .v for instantiation in my top module. If possible, give the constraints as well. 
ShallI use CAFE79xx_V2p6 for the no_os project in vitis? Please help me out in this process. 

Thank you 

  • 0
    TI__Genius 17831 points

    Hi,

    For the ZCU102 reference designs we recommend requesting access to the TI JESD204c IP, using the link below. Also, in the AFE79xx secure folder you will find an example reference design for the ZCU102 + AFE79xxEVM. For the SPI to be added you can follow the App Note linked below. 

    Please note that the TI204c-IP core file is only available in the .svp format. 

    https://www.ti.com/drr/opn/TI204C-IP 

    https://www.ti.com/lit/ug/sbau412a/sbau412a.pdf 

    Regards,

    David Chaparro 

  • 0 in reply to David Chaparro
    Prodigy 10 points

    Hi Sir, 
    I have tried this way with minor customization. Its failing to synthesize.
    Can I use JESD204C IP and JESD Phy IP available in Vivado to do the block design?
    How to interface between AFE7900 EVM and ZCU102? 
    ZCU102 has an FMC (consider HPC1). So, in the block design I'll route the signals to FMC. How establish this routing to AFE7900 EVM? Can I do it through vitis? If yes, please guide me through it. Or else, suggest the best way to do it.