Tool/software:
Hello,
I have implemented the clocking described in: RE: AFE7950: Clocking and SYSREF architecture to achieve deterministic latency JESD204B subclass 1
I am seeing a variable cadence on the Rx data valid in the FPGA on the receive side. I see primarily 1/8 data valid which is expected (clocked at 250 MHz, Rx rate of 31.25 MHz), but occasionally, I see 1/9 and 1/7 with a long-term average of 1/8.
1. Is this expected based on how I am sourcing the clocks to my FPGA?
2. Is there anything that you can tell me about the internal design of the encrypted IP core to help me to understand how to best interface with that design? (Async FIFO?, etc?)
Note that all my clocks are sourced by a single PLL and locked to the AFE7950 clock source as well.
Thank you,
Jesse