Tool/software:
Hello TI Support,
I am using the internal clock of the AFE evaluation board. I had a working design with these parameters:
FPGA refclk = 184.32 MHz
sysParams.FRef = 491.52
sysParams.FadcRx = 2949.12
sysParams.FadcFb = 2949.12
sysParams.Fdac = 2949.12*4
sysParams.ddcFactorRx = [16,16,16,16]
The free running clock was generated from sys_clk (184.32 MHz) and converted to 100 MHz with a Xilinx clock wizard. This configuration worked and the JESD link came up.
Now I tried to change to the following rates:
sysParams.FRef = 491.52
sysParams.FadcRx = 2457.6
sysParams.FadcFb = 2457.6
sysParams.Fdac = 2457.6*4
sysParams.ddcFactorRx = [16,16,16,16]
With this configuration, the FPGA refclk should be 153.6 MHz, but I measure about 155 MHz. The 100 MHz clock generated from sys_clk also comes out higher than expected. I also compiled a new GT IP for the FPGA with the 153.6 MHz reference, giving a JESD lane rate of 10137.6 MHz / 66. Even with this, the link does not come up, and Latte shows:
###########Device DAC JESD-RX 0 Link Status###########
Serdes-FIFO error for lane 0: 1
CS State TX0: 0b00000000 . It is expected to be 0b00000010
BUF State TX0: 0b00000001 . It is expected to be 0b00000011
Couldn't get the link up for device RX: 0; Alarms: 0x1000
###########Device DAC JESD-RX 1 Link Status###########
Serdes-FIFO error for lane 0: 1
CS State TX0: 0b00000000 . It is expected to be 0b00000010
BUF State TX0: 0b00000001 . It is expected to be 0b00000011
Couldn't get the link up for device RX: 1; Alarms: 0x1000
My goal is to be able to change ADC and DAC rates on the fly, adjust the GT QPLL on the FPGA side (through GT DRP), and keep the JESD link working with LMFS = 22810 (the older mapping, not the new one).
Could you please advise:
Is 153.6 MHz refclk valid for these rates with FRef = 491.52?
What is the right way to change the rates on the fly?