AFE7900EVM: Phase misalignment between Rx and feedback channels (AFE7900)

Part Number: AFE7900

Tool/software:

Hi,

We have a phase-critical application and are attempting to receive identical, phase-aligned signals on all channels by feeding the same phase-aligned source to each. While all Rx channels (RxA, RxB, RxC, RxD) show little to no phase difference between them, the feedback channels (FB1, FB2) are not phase aligned with the Rx channels. This is blocking our system performance.

Details and troubleshooting performed so far:

- The same input (identical phase) is fed to all channels.
- Rx channels A–D are properly aligned with each other (negligible phase difference).
- Feedback channels are not aligned with the Rx channels — the signals received on FB differ in phase from the corresponding Rx signals.
- We initially suspected sample alignment. At the FPGA side we shifted samples to attempt alignment; this produced near-alignment at one frequency but the phase misalignment reappeared when the input frequency changed. This suggests the problem is not simple sample misalignment but something frequency-dependent.
- All six signals (RxA–D, FB1, FB2) are phase aligned up to the input of the AFE7900, ensured by length-matched PCB traces and cables.
- Current AFE configuration:
    - LMFSHD = 14810
   - Lane muxing: 2 channels per lane
   - Number of JESD lanes = 3
   - Sample rate per channel = 122.88 MHz
   - DDC factor = 24


Questions:

1- Are the Rx and feedback channels inherently phase aligned, or are they independent/not aligned?
2- If they are intended to be phase aligned, which configuration settings should be used to achieve phase-aligned signals/data?

if helpful, I would be very glad to provide you with additional details.

Thanks in advance for your help.

Regards,
Noumeer

  • Hi Noumeer,

    The Rx and the FB channels are not identical in the part and share a different digital path so some phase difference is expected but this difference will be determenstic. My recommendation is to measure the difference then you can account for it either by updating the NCO phase or by adusjting the data in the FPGA.

    If you would like to adjust the phase of the NCO you can follow the sequence below, which shows how to update the phase of FB1's NCO.

    phaseNum=int(phaseOff/(360./2**16))


    device.writeReg(0x12,0x10)
    device.writeReg(0xE1,(phaseNum>>8)&0xFF)
    device.writeReg(0xE0,phaseNum&0xFF)
    device.writeReg(0x12,0x0)

    Regards,

    David Chaparro