Other Parts Discussed in Thread: AFE7950
Tool/software:
Dear Sir,
We are working on AFE7950 Script for both RX and FB channels working.
1.In ADC We are Planning to use the 4 nos of lanes for Rx channels(ie 4 channels) and 4 lanes for Fb channels(ie 2 channels)for that we are configuring both RX and FB channels as per the attached script.
We selected the JESD System mode as "1" for ADC channels and LMFSHdRx as-"48410" and LMFSHdFb as -"44210" . Kindly verify the below script for using both RX and FB channels and share your comments.
2.Then In HSDC Application ,Can we see both RX and FB results in One Initiation(INI) file or Firmware file in selection window? If not what is the INI file need to select for RX and FB as per our Configuration?
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_24410; Data Rate = 245.76M ---> To capture 4 RX channels
#In HSDC Pro ADC tab, Select AFE79xx_1x2FB_44210; Data Rate = 491.52M ---> To capture 2 FB channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = 1 # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 11700
sysParams.FadcRx = 2925
sysParams.FadcFb = 2925
sysParams.Fdac = 11700
sysParams.externalClockRx=True
sysParams.externalClockTx=True
sysParams.RRFMode = 0
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [24,24,24,24] #DDC decimation factor for RX A, B, C and D
sysParams.rxNco0 = [[2100,2100], #Band0, Band1 for RXA
[7200,7200], #Band0, Band1 for RXB
[1575,1575], #Band0, Band1 for RXC
[1176,1176]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [1,1]
sysParams.ddcFactorFb = [12,12] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [2100,1575] #Band0 for FB1 and FB2
##### TX #####
sysParams.txEnable = [0,0,0,0]
sysParams.ducFactorTx = [12,12,12,12] #DUC interpolation factor for TX A, B, C and D
sysParams.txNco0 = [[2500,2500], #Band0, Band1 for TXA
[5400,9500], #Band0, Band1 for TXB
[9500,9500], #Band0, Band1 for TXC
[9500,9500]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [1,1]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["48410","48410","48410","48410"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["44210","44210"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.jesdTxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2T,
# this should be [[1,0,2,3],[5,4,6,7]]
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["44210","44210","44210","44210"]
sysParams.jesdRxLaneMux = [0,1,2,3,4,5,6,7] # Enter which lanes you want in each location.
# For example, if you want to exchange the first two lines of each 2R
# this should be [[1,0,2,3],[5,4,6,7]]
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
# device.TOP.IO_WRAP.IO_WRAP.CFG_GPIO.pull_ctrl_gpio_34=3
# device.TOP.IO_WRAP.IO_WRAP.CFG_GPIO.odriv_ds_gpio_34=3
############## LMK Params ##############
lmkParams.pllEn = False #True
lmkParams.inputClk = 1462.5 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = False
lmkParams.sysrefFreq = 3.808594
setupParams.fpgaRefClk = 121.875 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
AFE.deviceBringup()
AFE.TOP.overrideTdd(15,3,15) # bit-wise; 4R,2F,4T
