AFE7950: JESD204C IP - RX Data Outputs Stuck at Zero in QuestaSim 2024.3 (Working in ModelSim/Vivado)

Tool/software:

JESD204C IP - RX Data Outputs Stuck at Zero in QuestaSim 2024.3 (Working in ModelSim/Vivado) 

Hello,,

I'm experiencing a simulation behavioral difference with the TI JESD204C IP encrypted model that appears to be specific to QuestaSim 2024.3_1. The same design simulates correctly in both ModelSim and Vivado XSim.

Environment:

• Simulator: QuestaSim Base Edition 2024.3_1 (64-bit, Linux)
• Previously working: ModelSim (unspecified version)
• Also working: Vivado XSim 2022.2
• Encrypted IP: TI_204c_IP_questasim.svp
• Target Device: Xilinx FPGA with GTH transceivers
• JESD204 Config: 8b10b encoding, 4 RX lanes, 4 TX lanes

Problem Description:

All RX data output signals (rx_lane_data_1 through rx_lane_data_4) remain stuck at zero throughout the simulation in QuestaSim, while all other aspects function correctly:

Working in QuestaSim:

• System clocks and resets
• JESD204 sync signal (active)
• Link valid signals (asserted)
• TX data path (non-zero values)
• Physical GTH lanes (rxp/rxn show activity)

Not working in QuestaSim:

• RX data outputs remain at 32'h00000000

Same testbench produces correct non-zero RX data in ModelSim and Vivado XSim.

Compilation Details:

Using standard Vivado-generated simulation flow: vopt -64 +acc=npr -L xil_defaultlib -L xpm -L XXXXXXX -L unisims_ver -L unimacro_ver -L secureip

Xilinx libraries compiled from Vivado 2020.2 for QuestaSim compatibility.

Questions:

1. Is there a known compatibility issue between TI_204c_IP_questasim.svp and QuestaSim 2024.3_1?
2. Is an updated .svp file available that addresses compatibility with newer QuestaSim versions?
3. Are there specific QuestaSim compilation options or settings required for the TI JESD204C IP that differ from ModelSim?
4. Could this be related to how QuestaSim Base Edition handles encrypted IP differently than previous ModelSim versions?

Additional Information:

The JESD204 link establishes successfully (verified by monitoring sync and link status), and the AFE model generates data on the serial lanes. The issue appears isolated to the data path output of the TI IP core itself - data enters but doesn't exit in QuestaSim, while the same code path works in ModelSim/Vivado.

Request:

Could you please advise on:

• Known issues with QuestaSim 2024.3 compatibility
• Updated encrypted IP models if available
• Recommended simulation settings for QuestaSim

This is blocking our design verification as we've migrated from ModelSim to QuestaSim.

Thank you for your support.