AFE7950EVM: AFE7950 + ZCU102 LMK & AFE7950 Configuring through FPGA

I am working on configuring the AFE7950EVM + ZCU102 setup, where both the LMK and AFE7950 are being configured through the FPGA. I need your support regarding a few points, which I have listed below:

1. SPI Communication:
   The LMK and AFE7950 SPI communications are functioning correctly. Also, the current drawn during configuration via the GUI matches the current observed when configuring the AFE7950EVM through the FPGA.

2. LMK Clock Issue:
   The 491.52-MHz LMK clock is currently not being generated. I will attach the relevant register details for your reference.

3. AFE7950 Reset Sequence:
   For resetting the AFE7950, I am using the sequence provided in the TI secure folder (the C code in tiAfe79_interface.c). Please confirm whether this sequence is sufficient for proper device configuration. I will also attach the main.c file showing the steps I am following.

4. JESD Reset Connections:
   I have connected the JESD_RSTn and JESD_TXRST pins to the master_reset_n, tx_reset_n, and rx_reset_n signals respectively in the TI_204c_IP_ref.sv file.main.c spiwrites_lmk.c spiwrites_AFE.c I kindly request you to review the above points and confirm whether the procedures are correct.
   Thank you, and I look forward to your feedback. Thanks & RegardsGuruthathathreya S