GC Product that best fits my Application

Hello,

The GC5016 as a 4 channel DDC, and another as a GC5016 4 channel DUC can be used as a repeater.  The TSW4100 EVM can demonstrate a single antenna

4channel repeater in these bandwidths.  The EVM uses a 14bit ADC sampling at 160Msps.  This could be modified to 120Msps which would fit your 2nd Nyquist zone

application.  The GC5016 for a 4 channel output with different IQ bandwidths would use the interleaved IQ mode for the DDC output, and DUC input.  We strongly recommend following the GC5016 IO Application Note and developing a full DDC BBIQ out to FPGA, and FS to FPGA to BBIQ DUC interface.  This will simplify the Sync tuning required for the repeater.

With a 120Mhz sample rate, the GC5016 would typically output a 20Mhz IQ rate for a 10Mhz channel, with a 50% BW filter.  The other 2nd set would utilize a 30Mhz IQ rate for a 15Mhz BW, a 10Mhz IQ rate for a 5Mhz BW, and a 10Mhz IQ rate for a 2.5Mhz BW.  These would all use a pair of GC5016s, based on the TSW4100 reference design.  Please contact Ken Chan (kenchan@ti.com) for the schematic, layout, and related files. 

Alternately the GC6016 could be used with more advanced data converters, and a TI DSP for control.  Ken could send you information about the multiple antenna, GC6016 version of the repeater GC6016 EVM.  The EVM kit is more expensive, but the GC6016 can provide wider bandwidths.

Regards,

Radio Joe

Hello,

In order to implement a 2 antenna, 4 channel per antenna repeater, you need 8 DDC and DUC channels. 

     a) using GC5016 - this method can support upto 4 different Bandwidths at any one configuration

            two heterodyne radio receivers RF to (60-120Mhz) IF

            two ADCs - 125Msps 14 bit CMOS interface, with output clock buffers

            two GC5016 as DDC - each having an single ADC input, MPU, and (4) 8bit CMOS DDC output interface (Frame, Clock, and 8 or 16 data)

            FPGA interface to receive Frame, 8bit data, Clock from each DDC channel IMSB, ILSB, QMSB, QLSB)

            FPGA interface to receive Frame and Clock from DUC, and output IQ 8 bit data (IMSB, ILSB, QMSB, QLSB) 

            two GC5016 as DUC - each having (4) 8data, Frame, Clock; MPU, and 16bitI, 16bitQ to CMOS DAC5688

            two DAC5688, two IQ Modulators, Synthesizer for Complex Direct Up Conversion

            some 16bit DSP(MPU) to load registers, software controlled SYNCA to each DDC, DUC  

    b) using GC6016 - this method supports two Bandwidths at any one configuration

            two heterodyne radio receivers RF to (0 - 120Mhz) IF

            two ADCs 250Msps, 14bit LVDS interface 61B49(41B49)

            one GC6016/GC5330 - two ADC interfaces, two DAC interfaces, two Nibble baseband Rx output (one for each BW), two Nibble baseband Tx input (one for each BW)

            16bit EMIFA (DSP MPU) interface to load registers and control startup

             FPGA that provides the LVDS interfaces for 4 data, 1 frame, 1 clock 2 sets for Tx, 2 sets for Rx, SyncA interface for startup clocked with DPD clock

             6748, L138 DSP to load registers (these are the two standard DSPs that have code for loading GC6016/GC5330)

             two DAC 3482 500Msps, 16 bit LVDS interfaces

Regards,

Radio Joe