Part Number: AFE7950
Hi,
We are using AFE7950 in a MIMO pulsed RADAR application. As part of bringing up a custom PCBA with AFE7950 on it, we are looping back the outputs of the D/A channels on the AFE7950 to its A/D inputs with a coaxial cable. In our pulsed RADAR application, the phase relationship of the return signal versus the transmitted signal is of absolute importance.
Unfortunately, in this loopback configuration, we are noticing substantial phase variability between the outgoing signal and the signal we measure on return. We have established that the phase of the digital signal we stimulated the D/A transmit side of the TI204C IP with is consistent from trigger to trigger. However, the return signal from the A/D appears to have an essentially random phase versus the outgoing signal. See the screenshots below. I've also attached our latte configuration. We are concerned that either the NCOs of the DUC / DDCs are free running versus the sample clock and / or that the decimation and interpolation counters are not being reset by the SYSREF pulse. We are operating in pulsed SYSREF mode. Halting the SYSREF pulses has minimal effect on the phase variability. Normally we send a SYSREF pulse just prior to sending an outgoing D/A pulse.
In each of these screenshots, you will notice that the phase of the captured signal varies widely. The signal shown is the RX signal from the AFE7950 ADC. The captures are made by triggering the logic analyzer on the rising edge of the signal which initiates the outgoing pulse to the TX half of the Ti204C IP. As I mention above, we've established consistent phase from the trigger to the launch of the outgoing pulse. However, we do not see consistent signal phase using the same trigger, on the returning signal, through the loopback COAX. Were the phase to be simply offset, this would be acceptable -- however it's inconsistent from pulse to pulse, which is severely concerning to our application.
We measured with an oscilloscope the timing of the SYSREF pulse arriving at the AFE7950 versus the AFE7950 reference clock -- we believe that the 50 ps setup and hold requirement is being met. However we do notice some variation in the insertion delay between asserting the SYNC pin on the LMK04828B (which is the reference clock and SYSREF origin for the AFE7950 and TI204C FPGA IP) and the SYSREF pulse appearing in the FPGA. We are using LMK04828B as our clocking IC. I've included below the Rx and Tx clock distribution diagrams. I've also attached our Latte config file.
############## Read me ##############
#In HSDC Pro DAC tab, Select AFE79xx_2x2TX_44210; Data Rate = 491.52M
#In HSDC Pro ADC tab, Select AFE79xx_2x2RX_44210; Data Rate = 491.52M ---> To capture 4 RX channels
sysParams=AFE.systemParams
sysParams.__init__();sysParams.chipVersion=chipVersion
setupParams.skipFpga = True # setup FPGA (TSW14J56) using HSDC Pro
############## Top Level ##############
sysParams.FRef = 500
sysParams.FadcRx = 3000
sysParams.FadcFb = 3000
sysParams.Fdac = 12000
sysParams.externalClockRx=False
sysParams.externalClockTx=False
############## Digital Chain ##############
##### RX #####
sysParams.ddcFactorRx = [12,12,12,12] #DDC decimation factor for RX A, B, C and D
#sysParams.rxNco0 = [[9500,9500], #Band0, Band1 for RXA
# [9500,9500], #Band0, Band1 for RXB
# [9500,9500], #Band0, Band1 for RXC
# [9500,9500]] #Band0, Band1 for RXD
sysParams.rxNco0 = [[4000,4000], #Band0, Band1 for RXA
[4000,4000], #Band0, Band1 for RXB
[4000,4000], #Band0, Band1 for RXC
[4000,4000]] #Band0, Band1 for RXD
##### FB #####
sysParams.fbEnable = [False,False]
sysParams.ddcFactorFb = [12,12] #DDC decimation factor for FB 1 and 2
sysParams.fbNco0 = [4000,4000] #Band0 for FB1 and FB2
##### TX #####
sysParams.ducFactorTx = [48,48,48,48] #DUC interpolation factor for TX A, B, C and D
#sysParams.txNco0 = [[9500,9500], #Band0, Band1 for TXA
# [9500,9500], #Band0, Band1 for TXB
# [9500,9500], #Band0, Band1 for TXC
# [9500,9500]] #Band0, Band1 for TXD
sysParams.txNco0 = [[4000,4000], #Band0, Band1 for TXA
[4000,4000], #Band0, Band1 for TXB
[4000,4000], #Band0, Band1 for TXC
[4000,4000]] #Band0, Band1 for TXD
############## JESD ##############
##### ADC-JESD #####
sysParams.jesdSystemMode= [3,3]
#SystemMode 0: 2R1F-FDD ; rx1-rx2-fb -fb
#SystemMode 1: 1R1F-FDD ; rx -rx -fb -fb
#SystemMode 2: 2R-FDD ; rx1-rx1-rx2-rx2
#SystemMode 3: 1R ; rx -rx -rx -rx
#SystemMode 4: 1F ; fb -fb- fb -fb
#SystemMode 5: 1R1F-TDD ; rx/fb-rx/fb-rx/fb-rx/fb
sysParams.jesdTxProtocol= [0,0] # 0 - 8b/10b encoding; 2 - 64b/66b encoding
sysParams.LMFSHdRx = ["24410","24410","24410","24410"]
# The 2nd and 4th are valid only for jesdSystemMode values in (0,2).
# For other modes, select 4 converter modes for 1st and 3rd.
sysParams.LMFSHdFb = ["22210","22210"]
sysParams.rxJesdTxScr = [True,True,True,True]
sysParams.fbJesdTxScr = [True,True]
sysParams.rxJesdTxK = [16,16,16,16]
sysParams.fbJesdTxK = [16,16]
sysParams.serdesTxLanePolarity =[0,0,0,0,1,0,1,0]
sysParams.jesdTxLaneMux = [2,3,6,7,0,1,4,5] # Enter which lanes you want in each location.
##### DAC-JESD #####
sysParams.jesdRxProtocol= [0,0]
sysParams.LMFSHdTx = ["24410","24410","24410","24410"]
sysParams.serdesRxLanePolarity = [0,0,0,0,0,1,1,1]
sysParams.jesdRxLaneMux = [4,5,0,1,7,6,2,3] # Enter which lanes you want in each location.
#sysParams.jesdRxLaneMux = [0,1,2,3,4,6,7,5] # Enter which lanes you want in each location.
sysParams.jesdRxRbd = [4, 4]
sysParams.jesdRxScr = [True,True,True,True]
sysParams.jesdRxK = [16,16,16,16]
##### JESD Common #####
sysParams.jesdABLvdsSync= True
sysParams.jesdCDLvdsSync= True
sysParams.syncLoopBack = True #JESD Sync signal is connected to FPGA
############## GPIO ##############
sysParams.gpioMapping = {
'H8': 'ADC_SYNC0',
'H7': 'ADC_SYNC1',
'N8': 'ADC_SYNC2',
'N7': 'ADC_SYNC3',
'H9': 'DAC_SYNC0',
'G9': 'DAC_SYNC1',
'N9': 'DAC_SYNC2',
'P9': 'DAC_SYNC3',
'P14': 'GLOBAL_PDN',
'K14': 'FBABTDD',
'R6': 'FBCDTDD',
'H15': ['TXATDD','TXBTDD'],
'V5': ['TXCTDD','TXDTDD'],
'E7': ['RXATDD','RXBTDD'],
'R15': ['RXCTDD','RXDTDD']}
sysParams.continuousSysref = False
############## LMK Params ##############
lmkParams.lmkVcoFreq = 3000
lmkParams.xtalFreq = 122.88
lmkParams.sysrefFreq = 3000/1024
lmkParams.pllEn = True
lmkParams.inputClk = 480 # Valid only when lmkParams.pllEn = False
lmkParams.lmkFrefClk = True
setupParams.fpgaRefClk = 125 # Should be equal to LaneRate/40 for TSW14J56
pathdz = "C:/Users/DougZielinski/Documents/Texas Instruments/AFE79xxLatte/lib/"
#lmkParams.pllEn = False
#lmkParams.inputClk = 1000 # Valid only when lmkParams.pllEn = False
#lmkParams.lmkFrefClk = True
#setupParams.fpgaRefClk = 125 # Should be equal to LaneRate/40 for TSW14J56
############## Logging ##############
#logDumpInst.setFileName(ASTERIX_DIR+DEVICES_DIR+r"\Afe79xxPg1.txt")
logDumpInst.setFileName(pathdz+r"\Afe79xxPg1.txt")
#logDumpInst.logFormat=0x21 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
#logDumpInst.logFormat=0x2000 #Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.logFormat=0x40 #Phil wants this one. Modify to 0x1 to save register scequence to log file. Script takes more time to execute.
logDumpInst.rewriteFile=1
logDumpInst.rewriteFileFormat4=1
device.optimizeWrites=0
device.rawWriteLogEn=1
device.delay_time = 0
#-------------------------------------------------------------------------------------------------#
#added by dz
#PhaseOffset=int(90/(360/2^16))
#PhaseOffset=int(32768)
#device.writeReg(0x12,0x2)
#device.writeReg(0xE1,(PhaseOffset>>8)&0xFF)
#device.writeReg(0xE0,PhaseOffset&0xFF)
#device.writeReg(0x12,0x0)
lmklogDumpInst=mLogDump.logDump(pathdz+r"\Afe79xxPg1_LMK.txt")
lmklogDumpInst.logFormat=0x21
lmk.logClassInst = lmklogDumpInst
lmk.rawWriteLogEn=1
setupParams.skipLmk = False
AFE.initializeConfig()
lmkParams.sysrefFreq = AFE.systemStatus.sysrefFreq
lmkParams.lmkPulseSysrefMode = True
AFE.LMK.lmkConfig()