Part Number: AFE8000EVM
Other Parts Discussed in Thread: AFE8000
Hi Team,
I am working for the Hong Kong local company named as Velenova Limited. We are using the AFE8000EVM as the RX only development. The development boards I am using are the AFE8000EVM and the AMD Zynq UltraScale+™ MPSoC ZCU102.
The FPGA development enAFE8000EVM_TI_JESD204C_187.5_12375_used(1).xlsx vironment is Vivado 2018.3, and the program uses the TI204C-IP v1.12 provided by the official website.
After powering on the device, I open AFE80xxCat. With the default configuration, I set the AFE frequency to 187.5 MHz, set the ADC JESD System Modes to 2R, use the JESD204C 64/66 communication protocol, and configure LMFS as 8-8-2-1-0. The input clock to the clock chip is 10 MHz with the PLL enabled. Then I click the "Device Bringup" button. Once the configuration is complete, I load the FPGA program. Using ILA, I observe that the valid signal is constantly high, indicating normal reception. However, the data is abnormal: most of the data is 0 (only one non-zero value in 32 repeated cycles, and 0 at all other times). This issue remains unchanged whether I set the AFE to output test data or input a signal from a signal source.
What could be the possible causes? Or how can I verify that the transmit and receive functions of the AFE8000 development board are working properly?
Attached is my AFE80xxCat configuration file.
