Please let me know about GC5018.

Hello,

The GC Studio software tool can be used to setup the GC5018 DDC.  The usage depends on the channel bandwidth.  In the "UMTS" mode there are 8 DDC channels.  The application with (2) 80Msps ADCs can be tested with an AFE8406 EVM, GC101, and GC Studio.  You need to contact Ken Chan (kenchan@ti.com) for EVM and/or GC Studio software availability.    (GC Studio runs on Win XP)

The standard setup can use an 80Mhz clock for DDC, and an 80Msps ADC input.  An alternate setup can use a 160Mhz clock for the DDC, and an 80Msps ADC input.

Note: AFE8406 is a dual 14bit ADC with the GC5018 DDC.  There is an AFE8406EVM, GC101, and GC Studio setup for testing AFE8406 (and also GC5018). 

Note: If the output IQ rate is faster than 10Msps the GC5016 (which only has 4 channels) can be used.

The GC5016 has the zero insertion (if the DDC clock and ADC input have an integer ratio > 1), front end processing, bus selection, Mixing, decimation filtering, and back end gain and AGC.

The GC Studio tool can be used to setup the programming for the GC5018 even if the hardware EVM is not connected (special operation of GC Studio with no hardware EVM).

There are UMTS examples with the TDM parallel output data bus for the 8 DDC channels.  

A suggested configuration Rx_InA, Rx_InB are the real ADC inputs at 76.8Msps, DDC clock is 153.6Msps

                                                 front end AGC is bypassed

                                                 Rx bus is distributed to the 8 DDC channels (A -> 0,1,2,3) (B -> 4,5,6,7) at 76.8Mhz rate 

                                                 tuning set for -20Mhz , after the tuning the delay adjustment the zero pad interpolates by 2

                                                 CIC decimation is set for 10, CFIR decimation is set for 2, PFIR decimation is set for 1, the output decimation feature is not used

                                                 CFIR filter -> 15.36Mhz input rate, Fpass 2.5Mhz, Fstop 4.1Mhz, 36 taps, 5tap High Pass CIC correction -> 40 taps, decimate by 2

                                                 PFIR filter -> can be a Low pass for LTE5, or a Root Raised Cosine Filter .22 for UMTS - 64 taps

Note: Programming the filter taps needs to follow the datasheet, as there are specific methods for programming < 64 taps. 

Regards,

Radio Joe

Hello.

Thank you for advising instantly.

I was allowed to consult by the following contents at Mr. Chan who introduced.

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【Back ground】
I would like to input ADC (80Msps) into GC5018, and to process nothing within a device like attachment,
but to pass 80Msps signal to FPGA (DDC is bypassed) as it is.

【Question-1】
For the purpose, what kind of setup should be carried out?
And please let me know a setup which bypasses DDC.

【Question-2】
Please let me know the meaning of "par_recv_chan(3:0)".
（Datesheet P57）
For example, when it is set as "1", what kind of output is carried out?
I want a timing diagram, if it can do.
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There is hope that a customer will be saved if GC5016 is used before and the above-mentioned setup can respond by the software.
Is a setup with the software tool of GC5016 possible in GC5018?
since I will send the data of GC5016 before set up by the customer if possible -- examination -- I would appreciate your favor.
In addition, application will be for radars and quantity will be a year in ten sets.

As mentioned above, I need your help well.

Sincerely yours,

Satoshi

Hello,

The GC5018 has several different modes of operation.  The DDC can be operated in

   a) CDMA mode - there are 16 DDC channels, the minimum decimation is 16.  Given an Rx clock rate of 160Mhz, using an 80%bandwidth filter, no output decimation each channel can have a 8Mhz output BW

   b) UMTS mode - there are 4(double PFIR) or 8 DDC channels, the minimum decimation is 8.  Given an Rx clock rate of 160Mhz, using an 80% bandwidth filter, no output decimation each channel can have a 16Mhz output BW

the CFIR and PFIR filter design for the GC5018 is based on the calculations for the number of filter taps, see page 24 and 29 of the GC5018 datasheet. 

The DDC output can be parallel(any DDC mode), 2wire serial(CDMA), 4 wire serial (UMTS), or 8 wire serial (UMTS double PFIR).  Note the DDC output maximum rate is based on the Mode, CIC decimation.  The maximum rate for UMTS mode is 160/8 = 20Msps complex. 

If you want a DDC output, with a complex rate higher than 20Msps, (ie smaller decimation than 8) the choices are the GC5016 and GC6016. 

The GC5018 has a special set of pins used for testing, called the test bus.  The RxinC, RxinD, DVGAC and DVGAD pins can be sent to a test logic analyzer or FPGA connector.    See table on page 108 of the datasheet.  section 5.1 of page 122.  The test bus can monitor one channel / signal at a time, and can send a specific signal to these pins.  Ken Chan can contact the internal designers (part designed in Tempe group) to get timing diagrams for the Test Bus.   

If you want to get the ADC output for test, you can use the test bus.  If you want to use the DDC output, the maximum IQ rate is 20Msps. 

The other question is the number of DDC outputs that are output on the parallel output bus.  see page 57 of the datasheet. 

par_recv_chan(3:0) :Selects the number of channels to be output over the parallel interface, from 1 to 16 channels, you would subtract one from the total number of DDC channels being output.

The GC5018 parallel output bus is the upper 16 bits of I and Q, an output clock, and the Rx_sync_out to indicate the first DDC output channel.  Figure 3-33 shows a timing diagram of the parallel output interface (page 42 of the datasheet). 

The GC Studio software can be used with the AFE8406 plug in card, GC101, to program and operate the GC5018 DDC.  An external clock board is also needed.  The GC Studio software can be used without the EVM hardware to create a programming file. 

Regards,

Radio Joe