GC6016 application for SDR

Jim,

As described in the GC6016 datasheet, table 22 note 1, there is a minimum PLL output requirement of 400MHz. This limitation prevents the chip to support a baseband interface sample rate of 96KSPS. The minimum baseband interface rate that can be supported is 2.4576MSPS. For your application, it will require an additional interpolator/decimator to resample the 96KSPS data to 2.4576MSPS.

Kyle

Kyle,

Thanks for the quick response.  I believe we will be talking on a conference call tomorrow, but I have some confusion about this requirement based on a previous related post (see below).  The datasheet does not have any discusion of the PLL or how it relates to the DPD clock and BB clock.  Can you elaborate?

Also, the part appears to have the ability to decimate by a maximum factor of 98,304 ( BDC x16, CIC x 3, FARROW x 1024, FIR  x 2) so what is the purpose of this if the minimum BB rate is or the order of 2 MSPS?

http://e2e.ti.com/support/rf__digital_radio/digital_radio_gc_products/f/220/t/88863.aspx

Thanks for your help.

Jim Tiffany

jim.tiffany@entropixllc.com