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TRF3720 testing

Longchang Chen
Intellectual 1350 points
Other Parts Discussed in Thread: TRF3765

does the step frequency is channel spacing of customer? now my customer want to set it as 0.1M, and input reference is 153.6M, and output RF is 2496M, and i tried it, but couldn't got lock of TRF3720? why it is that? like this customer need, pls suggest suitable step frequency. 

  • 0
    TI__Expert 3300 points

    The loop filter must be designed to match the pfd frequency. A PLL synthesizer will not lock unless the loop filter and pfd frequency are matched. The EVM ships with the loop filter in table 7 for 1.6MHz pfd frequency.

    In integer mode, frequency step size is determined by the pfd frequency. Step size described by equation 4 on page 42 of the datasheet. With RF frequency 2496MHz, LO_DIV_SEL = 1. Therefore

    fSTEPSIZE = fPFD * PLL_DIV_SEL

    To achieve a stepsize of 0.1MHz, fPFD would have to be quite small and the loop filter would also have to be redesigned to match fPFD.

    In fractional mode, stepsize of 0.1MHz is very easy. To get the best fractional mode performance, please use a pfd frequency of 30.72MHz with the 30.72MHz loop filter from table 7.

    If you continue to have problems, please consult Table 5, Ttroubleshooting Sequences, in the TRF3765 EVM User's Guide at http://www.ti.com/lit/ug/slwu076/slwu076.pdf.

  • 0 in reply to Pete Hanish
    TI__Intellectual 1350 points

    where is the table? is in D/S of TRF3720 or user guide of TRF3720 EVK, i haven't found it. as your description, when i set the 0.1M step and 153.6M ref, 2496M output in TRF3720 GUI SW, and cal it, but i couldn't got 30.72M Fpfd, the PFD is auto-cal out. how to set it?