GC4016 multiboard synchronisation

Hello,

Normally the GC4016 has several decimation stages: CIC,CFIR, PFIR, Resampler.  Following section 1.2.4.2, there are two split IQ channels, with special

delay controls so that channels AB handles the even samples, and CD handles the odd samples.  If the CIC programming 'N' ==  5, the total decimation of the channel is two splitIQ sections that decimate by 18, the two polyphase combinations are combined to produce a decimation of 9.

 When trying to synchronize two devices, that have a common clock, the clock quality and SIA (or SIB) used for synchronization must have good signal quality.

The AC characteristics have specific clock transition and duty cycle requirements.  the SIA (or SIB) signal needs to meet the Tsu and Thi requirements to the clock, typically it is a logic '1', goes to a logic '0', for one clock period, and returns to the logic '1' state.  The clock where the sync changes from  0 -> 1 is the release of Sync.  If the Sync is more than 1 clock period as a logic low, the synchronization does not work the same way, as the sync low for more than 1 clock is a different behavior.

section 1.2.12.1 for synchronizing multiple GC4016s should have the SIA input of all GC4016s and the Ck as common signals.  The SO can be used to measure the sync event on each GC4016.  You would tie the SO sync to the SIA input, so that you can monitor both signals. 

The ADC digital output, used for the A,B,C,D input needs to be checked that its outputs meet the Tsu and Thi input requirements of the GC4016. 

We have no method to test multiple GC4016s in the lab.  If you use the internal 1/2 scale DC input, you can collect the output from the SOB trigger, each device should have the same output.   The NCO has to be retuned for an inband signal, if the input is ia DC constant. 

The GC4016 Ck has a larger capacitive load than other CMOS inputs, it is not normally driven from the ADC output, it is buffered, and then thevenin (pull up/pull down) terminated. 

Regards,

Radio Joe

Hello,

Thank you for all the support. We have gone through the probable reasons listed in your reply.

The quality of the clock used for deriving the SIA is of very good quality. The clock for both the boards is sourced from a single Rubidium oscillator. Also we have verified SIA signals of both the boards. The raising edge of the SIA signal of the two boards are perfectly aligned..

The second point in your reply is about the pulse width and the negation of the SIA signal. From the GC4016 datasheet it is clear that the chip will go into synch process when the raising edge of CK senses SIA going HIGH. The datasheet does not mention what should be the pulse width of SIA should be.

As per the datasheet, the synchronization procedure should be as below:

1. The Chip should be placed in RESET by the processor by writing into the chip registers.
2. The processor should make ONE_SHOT as high
3. The external SYNC signal (SIA) should be taken LOW
4. The Chip should be release from RESET by the processor by writing into the chip registers.
5. The processor should make ONE_SHOT as low
6. The SYNC signal (SIA)should be taken HIGH (synchronously for both the boards).

As may be observed from the above, the synch process involves programming the registers (a software process) and issuing SIA in a synchronized manner (hardware). As software does not work in real time, the SIA must be longer than one clock period to make sure that the above sequence is followed. Also, the DDC Chips appear to read the raising edge of the SIA as  the samples at the output of the DDC are 0’s for about 400 output clock cycles and then the input signal is appearing

The third point is about the data input to the DDC. The DDC input is coming from ADC. We have followed standard design practices where in the source gives data w.r.t raising edge and the receiver reads the data w.r.t falling edge. Also, if this is a issue, the output of the DDC should have aberrations. However we always found the DDC output to be OK (when we give sine wave signal to the DDC, the DDC output is also perfect sine signal). The only issue is that the sine wave signal output of the DDC Chips on the two boards are not phase aligned.

We have another observation. When we tune NCO to 0Hz in both the boards, the output of the DDC is perfectly aligned. From this it appears that the NCO phase is not aligned among the two boards.

Registers are programmed in below sequence:

CFIR and PFIR of all 4 channels  = 150%

Tuning phase: ch1 =0,ch2 =0x4000,ch3 =0,ch4 =0x4000

Tuning freq: 2.5MHz for all channels

Input selection:ch1=A, ch2 =B, ch3=C, ch4 =D

GLOBAL RESET = 0XF0

DIAG_SYNC = 7

OUTPUT_SYNC = 4

4_BIT_ADDRESS = 0

DIFF_IN=0

DIAG_SOURCE = 0

COUNTER_SYNC =2

COUNT_TEST =0

OS_MODE = 1

ONE_SHOT = 0

CNT = 9

---------------------CH 0-----------------------

SHIFT = 5

USE_SHIFT = 1

CH_RESET = 0

PHASE_SYNC = 2

FREQ_SYNC = 2

NCO_SYNC = 2

DITHER_SYNC = 2

NZEROS = 0

ZPAD_SYNC = 2

ZPAD_EN = 0

DEC_SYNC = 2

FLUSH_SYNC = 2

DEC = 9

GAIN_SYNC = 7

SCALE = 4

BIG_SCALE = 7
MIX20B =1

NEG_CTL =0

SPLITIQ =1

IONLY =1

QONLY = 0

NO_SYM_CFIR = 0

QDLY_CFIR = 0

IDLY_CFIR = 0

COARSE = 0

TEST = 0

NO_SYM_PFIR = 0

QDLY_PFIR = 1

IDLY_PFIR = 0

PEAK_SELECT = 0

INPUT_SEL = 0

SEL_AB = 0

INPUT_MODE = 0

MSB_POL = 0

PEAK_SYNC =7

PEAK_THRESHOLD = 3

PEAK_MODE = 0

NC =4

NF = 0

RES_SYNC =2

NM = 6

NO_SYM_RES = 1

FILTER_SEL_REG =0

FINAL_SHIFT = 5

ROUND = 1

TAG_22 = 0

CH_MAP_REG =0

RATIO_SYNC =7

RESAMPLER_CLK_DIVIDE_REG =0

RATIO_MAP_REG =0

Similarly ch1,2,3 are loaded

ONE_SHOT = 1

GLOBAL RESET = 0

1msec delay

ONE_SHOT =0