I have an application with the following parameters:
DDC mode, Ext Clock = 76.8MHz, cic_dec=5, fir_dec =2, pins=8, bits=8, sck_div=4, routf_tdm=0, routf_iqmux=1
This application is working correctly. I would like to go to 16bits of output but I am constrained by the fact that only 8 pins are connected on each channel, and the sck_div is limited to be >=4 for the FPGA to be able to keep up with the output. As far as I understand, this means that I cannot do 16bits because sck_div would have to be less than 4. Here are my questions: When I enable splitiq, does the I data show up on the channel A/C ouput and the Q data show up on the B/D output? If this is true, does clocking the data take only 2 clock cycles instead of 4? In other words, is it possible to use split IQ mode to reduce the number of clocks necessary to output the data, or do I still need 4 clock cycles to get the 16bits of I and 16bits of Q data out?
Regards,
