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ADC clock on TSW4100

Bjoern19538
Prodigy 30 points
Other Parts Discussed in Thread: ADS5545

I have noticed that in the factory configuration of the TSW4200  the clock for the ADS5545 is generated single ended in the CDMC7005 then buffered, filtered and then converted in a differential signal.

What is the reason for this?  Why is the clock not simply  generated differentially and  then routed directly to the ADC?

Since we are design a similar system this would be important to know.

 

Best regards

Bjoern

  • 0
    TI__Mastermind 37500 points

    Hello Bjoern,

    In your system design, you would need to know the amount of allowed jitter for the ADC clock. 

    Some systems that use a lower IF frequency, or have relaxed ADC clock jitter requirements can use the direct differential connection from the clock solution to the ADC.

    Some customers need further analog filtering of the ADC clock, to lower the RMS jitter, most of this filtering is done with a bandpass filter, on a single ended clock.  The single ended clock is then converted back to differential for the ADC clock input.

    Regards,

    Radio Joe

     

  • 0 in reply to Radio-Joe
    Prodigy 120 points

    In the tsw4100 there is a very tight bandpass filter that is obsolete. Also the data sheet is not available. Is there a known working replacement part for it ? (TF2-G0EC2).

    according to your answer, and using the same ti components (adc,ddc,duc,dac), this part is critical !

    Thanks

  • 0 in reply to jacob sarusi
    TI__Mastermind 37500 points

    Hello Jacob,

    I have sent an email to Ken Chan (kenchan@ti.com) related to your request for more TSW4100 information.  The ADC clock filter is based on reducing jitter on the ADC sample clock.

    There is an application note SNAA036A, that can help in selecting a bandpass filter.    Depending on your budget for the receive SNR, you may be able to use the LvPECL differential clock without a filter from the Clock solution.  The 14bit ADC for the input to the GC5016 must have, 2s complement output, usually requires a buffer for the ADC clock output, and have 3.3v CMOS signalling type. 

    The clock solution and bandpass filter need to meet your SNR requirements

    SNR(dBFS) = –20log(2πfinσ), example: 140Mhz IF, 60dbc -> approx 1-2ps jitter

    Regards,

    Radio Joe