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GC5016 DUC output timing

ruchi johari
Prodigy 190 points

Hi Joe

 

1) Referring to the SLWA037.pdf Input& output timing document , figure 26  the Th(o) & Td  delays are not referenced to the positive edge of CK clock whereas in the datsaheet definition of these two timing parameters under the heading AC characteristics (page 4 , datasheet GC5016) both data output hold and data output delay are measured from the rising edge of CK. If you could help understand the same.

 

 

  • 0
    TI__Mastermind 37500 points

    Hello Ruchi,

    The GC5016 DUC output for Td and Tho should be referenced to the Ck input clock.  The data is valid after the Td delay, and upto the next Ck + Tho delay. 

    The GC5016 Ck clock for output, and the receiving clock need to meet the allowed timing margin for the real or parallel complex output shown in Figure 26.  The receive clock may be skewed relative to the GC5016 Ck to meet the receiver Tsu and Thi timing.

    Regards,

    Radio Joe