GC5316 recieve output interface

Hello,

1) serial clock divider - Section 2.6, page 24 Figure 19 discusses that the 2 wire serial output for CDMA, and 4 wire serial output for UMTS is based on the divided clock value,

and the Frame strobe interval.  The clock divider programming pser_recv_clkdiv can be set for a full rate output.  Depending on the decimation, and the number of output bits

there may be idle time that would allow the clock to be divided.  See equation at the bottom of page 23. 

2) frame strobe for each DDC output

Figure 1, page 3 shows the rx_sync_out# as the Frame Sync for each 4 DDC (CDMA) outputs.

   Rxsyncout0 - rxout0, rxout1

   Rxsyncout1 - rxout2, rxout3

   Rxsyncout2 - rxout4, rxout5

   Rxsyncout3 - rxout6, rxout7

   Rxsyncout4 - rxout8, rxout9

   Rxsyncout5 - rxout10, rxout11

3) The rx_sync_out width and the note at the bottom of Figure 19 are used for the FPGA receiver logic.  You could program the RxSyncout to be output earlier than the MSB of the data, depending on the receiver logic.  Typical application is to set the Sync output width to 1 clock.  The 0->1 transition of the registered sync output identifies the MSB of the serial data stream output.

4) Figure 19, rx_sync_out width is based on Rx clocks.

5) On Figure 19, at the bottom, the clock is programmed for divide by 2 pser_recv_clkdiv = 1. 

6) Yes

If you have a decimation of 32, and you have 16bit data, you could divide the serial clock output by 2.

                                                 32, and you have 18bit data, you would need to use a full clock rate output.

The key is that the Frame strobe output occurs once every decimation input clocks.

Regards,

Radio Joe